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Lines Matching refs:OpEntry

1654   const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1664           TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1666   if (OpEntry.OpSignExtend) {
1667     if (OpEntry.IsOpSigned)
1669               TII.get(OpEntry.OpSignExtend));
1695           TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1707       OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1725         .addReg(OpEntry.DivRemResultReg);