Lines Matching defs:POWER
84 /* Opcode is defined for the POWER (RS/6000) architecture. */
98 but it also supports many additional POWER instructions. */
101 /* Opcode is supported in both the Power and PowerPC architectures
105 /* Opcode is supported for any Power or PowerPC platform (this is
263 only supported on the PowerPC, not the POWER. */
296 hack is needed because the Power rotate instructions can take
322 /* The POWER and PowerPC assemblers use a few macros. We keep them
588 /* The FL1 field in a POWER SC form instruction. */
594 /* The FL2 field in a POWER SC form instruction. */
635 /* The LEV field in a POWER SVC form instruction. */
802 /* The SV field in a POWER SC form instruction. */
1972 #define POWER PPC_OPCODE_POWER
2898 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2899 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2901 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
3142 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3589 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3788 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3850 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3853 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
4177 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4183 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4364 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
5089 in both big and little endian mode and also for the POWER (RS/6000)
5190 /* Print a POWER (RS/6000) instruction. */
5198 /* Extract the operand value from the PowerPC or POWER instruction. */
5248 /* Print a PowerPC or POWER instruction. */
