Lines Matching refs:rE
57 * FSAVE does not re-initialise the FPU; it should do
71 /* Notes re address size overrides (0x67).
201 /* The IRSB* into which we're generating code. */
1651 /* Exclude OP and NDEP from definedness checking. We're only
1676 checking. We're only interested in DEP1 and DEP2. */
1697 /* Exclude OP and NDEP from definedness checking. We're only
3795 /* we're optimists :-) */
5536 /* declare we're reading memory */
5541 /* declare we're writing guest state */
5632 /* declare we're writing memory */
5637 /* declare we're reading guest state */
6203 /* declare that we're reading memory */
6231 /* declare we're writing memory */
6317 /* declare we're writing guest state */
6535 /* declare we're reading memory */
6540 /* declare we're writing guest state */
6615 /* declare we're writing memory */
6620 /* declare we're reading guest state */
8013 /* Mask out upper bits of the shift amount, since we're doing a
10092 UInt rE = eregOfRexRM(pfx,modrm);
10093 assign( sV, getYMMReg(rE) );
10096 DIP("vpshufd $%d,%s,%s\n", order, nameYMMReg(rE), nameYMMReg(rG));
10328 UInt rE = eregOfRexRM(pfx,modrm);
10329 assign( f32lo, getXMMRegLane32F(rE, 0) );
10330 assign( f32hi, getXMMRegLane32F(rE, 1) );
10333 isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
10365 UInt rE = eregOfRexRM(pfx,modrm);
10366 assign( f32_0, getXMMRegLane32F(rE, 0) );
10367 assign( f32_1, getXMMRegLane32F(rE, 1) );
10368 assign( f32_2, getXMMRegLane32F(rE, 2) );
10369 assign( f32_3, getXMMRegLane32F(rE, 3) );
10371 DIP("vcvtps2pd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
10404 UInt rE = eregOfRexRM(pfx,modrm);
10405 assign( argV, getXMMReg(rE) );
10408 nameXMMReg(rE), nameXMMReg(rG));
10451 UInt rE = eregOfRexRM(pfx,modrm);
10452 assign( argV, getXMMReg(rE) );
10455 isAvx ? "v" : "", r2zero ? "t" : "", nameXMMReg(rE), nameXMMReg(rG));
10501 UInt rE = eregOfRexRM(pfx,modrm);
10502 assign( argV, getYMMReg(rE) );
10505 r2zero ? "t" : "", nameYMMReg(rE), nameYMMReg(rG));
10553 UInt rE = eregOfRexRM(pfx,modrm);
10554 assign( argV, getXMMReg(rE) );
10557 isAvx ? "v" : "", r2zero ? "t" : "", nameXMMReg(rE), nameXMMReg(rG));
10608 UInt rE = eregOfRexRM(pfx,modrm);
10609 assign( argV, getYMMReg(rE) );
10612 r2zero ? "t" : "", nameYMMReg(rE), nameXMMReg(rG));
10662 UInt rE = eregOfRexRM(pfx,modrm);
10663 assign( argV, getXMMReg(rE) );
10666 isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
10710 UInt rE = eregOfRexRM(pfx,modrm);
10711 assign( argV, getYMMReg(rE) );
10713 DIP("vcvtdq2ps %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
10755 UInt rE = eregOfRexRM(pfx,modrm);
10759 assign(t0, getXMMReg(rE));
10762 DIP("%spmovmskb %s,%s\n", isAvx ? "v" : "", nameXMMReg(rE),
10774 UInt rE = eregOfRexRM(pfx,modrm);
10780 assign(t0, getYMMRegLane128(rE, 0));
10781 assign(t1, getYMMRegLane128(rE, 1));
10785 DIP("vpmovmskb %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
11241 UInt rE = eregOfRexRM(pfx,modrm);
11242 assign( sV, getXMMReg(rE) );
11247 imm8, nameXMMReg(rE), nameXMMReg(rG));
11295 UInt rE = eregOfRexRM(pfx,modrm);
11296 assign( sV, getYMMReg(rE) );
11300 imm8, nameYMMReg(rE), nameYMMReg(rG));
11337 UInt rE = eregOfRexRM(pfx,modrm);
11338 assign(sV, getXMMReg(rE));
11342 (Int)imm8, nameXMMReg(rE), nameIReg32(rG));
11376 UInt rE = eregOfRexRM(pfx,modrm);
11377 assign( arg64, getXMMRegLane64(rE, 0) );
11379 DIP("%scvtdq2pd %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
11560 UInt rE = eregOfRexRM(pfx,modrm);
11566 here since that can't be re-emitted as SSE2 code - no such
11588 nameXMMReg(rE), nameXMMReg(rG) );
11598 UInt rE = eregOfRexRM(pfx,modrm);
11605 binop(Iop_Shr32, getXMMRegLane32(rE,0), mkU8(31)),
11608 binop(Iop_Shr32, getXMMRegLane32(rE,1), mkU8(30)),
11611 binop(Iop_Shr32, getXMMRegLane32(rE,2), mkU8(29)),
11614 binop(Iop_Shr32, getXMMRegLane32(rE,3), mkU8(28)),
11620 nameXMMReg(rE), nameIReg32(rG));
11629 UInt rE = eregOfRexRM(pfx,modrm);
11640 binop(Iop_Shr32, getYMMRegLane32(rE,0), mkU8(31)),
11643 binop(Iop_Shr32, getYMMRegLane32(rE,1), mkU8(30)),
11646 binop(Iop_Shr32, getYMMRegLane32(rE,2), mkU8(29)),
11649 binop(Iop_Shr32, getYMMRegLane32(rE,3), mkU8(28)),
11652 binop(Iop_Shr32, getYMMRegLane32(rE,4), mkU8(27)),
11655 binop(Iop_Shr32, getYMMRegLane32(rE,5), mkU8(26)),
11658 binop(Iop_Shr32, getYMMRegLane32(rE,6), mkU8(25)),
11661 binop(Iop_Shr32, getYMMRegLane32(rE,7), mkU8(24)),
11670 DIP("vmovmskps %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
11680 UInt rE = eregOfRexRM(pfx,modrm);
11685 binop(Iop_Shr32, getXMMRegLane32(rE,1), mkU8(31)),
11688 binop(Iop_Shr32, getXMMRegLane32(rE,3), mkU8(30)),
11692 nameXMMReg(rE), nameIReg32(rG));
11701 UInt rE = eregOfRexRM(pfx,modrm);
11708 binop(Iop_Shr32, getYMMRegLane32(rE,1), mkU8(31)),
11711 binop(Iop_Shr32, getYMMRegLane32(rE,3), mkU8(30)),
11714 binop(Iop_Shr32, getYMMRegLane32(rE,5), mkU8(29)),
11717 binop(Iop_Shr32, getYMMRegLane32(rE,7), mkU8(28)),
11722 DIP("vmovmskps %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
12008 UInt rE = eregOfRexRM(pfx,modrm);
12009 assign( sV, getXMMReg(rE) );
12012 nameXMMReg(rE), nameXMMReg(rG));
12036 UInt rE = eregOfRexRM(pfx,modrm);
12037 assign( sV, getXMMReg(rE) );
12040 nameXMMReg(rE), nameXMMReg(rG));
13586 /* declare we're writing memory */
13591 /* declare we're reading guest state */
13637 As with FXSAVE above we ignore the value of REX.W since we're
13664 /* declare we're reading memory */
13669 /* declare we're writing guest state */
13814 UInt rE = eregOfRexRM(pfx,modrm);
13815 assign(t4, getIReg16(rE));
13819 (Int)lane, nameIReg16(rE), nameXMMReg(rG));
13896 UInt rE = eregOfRexRM(pfx,modrm);
13897 assign( sV, getXMMReg(rE) );
13900 DIP("shufps $%d,%s,%s\n", imm8, nameXMMReg(rE), nameXMMReg(rG));
14416 UInt rE = eregOfRexRM(pfx,modrm);
14417 assign( sV, getXMMReg(rE) );
14419 DIP("pmuludq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
14472 UInt rE = eregOfRexRM(pfx,modrm);
14473 assign( sV, getXMMReg(rE) );
14475 DIP("pmaddwd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
14505 UInt rE = eregOfRexRM(pfx,modrm);
14506 assign( sV, getXMMReg(rE) );
14508 DIP("psadbw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
14640 UInt rE = eregOfRexRM(pfx,modrm);
14641 assign( sV, getXMMReg(rE) );
14643 isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
14670 UInt rE = eregOfRexRM(pfx,modrm);
14671 DIP("vmovddup %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
14673 assign ( d0, getYMMRegLane64(rE, 0) );
14674 assign ( d1, getYMMRegLane64(rE, 2) );
14703 UInt rE = eregOfRexRM(pfx,modrm);
14704 assign( sV, getXMMReg(rE) );
14706 rE), nameXMMReg(rG));
14737 UInt rE = eregOfRexRM(pfx,modrm);
14738 assign( sV, getYMMReg(rE) );
14740 isL ? 'l' : 'h', nameYMMReg(rE), nameYMMReg(rG));
14859 UInt rE = eregOfRexRM(pfx,modrm);
14860 assign( eV, getXMMReg(rE) );
14861 DIP("h%sps %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
14884 UInt rE = eregOfRexRM(pfx,modrm);
14885 assign( eV, getXMMReg(rE) );
14886 DIP("h%spd %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
14909 UInt rE = eregOfRexRM(pfx,modrm);
14910 assign( eV, getXMMReg(rE) );
14911 DIP("addsubpd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
14933 UInt rE = eregOfRexRM(pfx,modrm);
14934 assign( eV, getXMMReg(rE) );
14935 DIP("addsubps %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
15132 UInt rE = eregOfRexRM(pfx,modrm);
15133 assign( sV, getXMMReg(rE) );
15135 nameXMMReg(rE), nameXMMReg(rG));
15203 UInt rE = eregOfRexRM(pfx,modrm);
15204 assign( sV, getYMMReg(rE) );
15205 DIP("vph%s %s,%s\n", str, nameYMMReg(rE), nameYMMReg(rG));
15468 UInt rE = eregOfRexRM(pfx,modrm);
15469 assign( sV, getXMMReg(rE) );
15471 DIP("pmaddubsw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
15992 which we can only decode if we're sure this is a BMI1 capable cpu
16052 which we can only decode if we're sure this is an AMD cpu
16199 UInt rE = eregOfRexRM(pfx, modrm);
16200 assign(vecE, getXMMReg(rE));
16204 name, nameXMMReg(rIS4), nameXMMReg(rE),
16238 UInt rE = eregOfRexRM(pfx, modrm);
16239 assign(vecE, getYMMReg(rE));
16243 name, nameYMMReg(rIS4), nameYMMReg(rE),
16374 UInt rE = eregOfRexRM(pfx, modrm);
16375 assign(vecE, getXMMReg(rE));
16380 nameXMMReg(rE), nameXMMReg(rG) );
16427 UInt rE = eregOfRexRM(pfx, modrm);
16428 assign(vecE, getYMMReg(rE));
16432 nameYMMReg(rE), nameYMMReg(rG) );
16485 UInt rE = eregOfRexRM(pfx, modrm);
16486 assign( srcVec, getXMMReg(rE) );
16488 DIP( "%spmov%cxbw %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
16527 UInt rE = eregOfRexRM(pfx, modrm);
16528 assign( srcVec, getXMMReg(rE) );
16530 DIP( "vpmov%cxbw %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
16569 UInt rE = eregOfRexRM(pfx, modrm);
16570 assign( srcVec, getXMMReg(rE) );
16572 DIP( "%spmov%cxwd %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
16607 UInt rE = eregOfRexRM(pfx, modrm);
16608 assign( srcVec, getXMMReg(rE) );
16610 DIP( "vpmov%cxwd %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
16646 UInt rE = eregOfRexRM(pfx, modrm);
16647 assign( srcBytes, getXMMRegLane32( rE, 0 ) );
16649 DIP( "%spmovsxwq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
16679 UInt rE = eregOfRexRM(pfx, modrm);
16680 assign( srcBytes, getXMMRegLane64( rE, 0 ) );
16682 DIP( "vpmovsxwq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
16714 UInt rE = eregOfRexRM(pfx, modrm);
16715 assign( srcVec, getXMMReg(rE) );
16717 DIP( "%spmovzxwq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
16749 UInt rE = eregOfRexRM(pfx, modrm);
16750 assign( srcVec, getXMMReg(rE) );
16752 DIP( "vpmovzxwq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
16795 UInt rE = eregOfRexRM(pfx, modrm);
16796 assign( srcVec, getXMMReg(rE) );
16799 DIP( "%spmov%cxdq %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
16840 UInt rE = eregOfRexRM(pfx, modrm);
16841 assign( srcVec, getXMMReg(rE) );
16843 DIP( "vpmov%cxdq %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
16890 UInt rE = eregOfRexRM(pfx, modrm);
16891 assign( srcVec, getXMMReg(rE) );
16893 DIP( "%spmov%cxbd %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
16932 UInt rE = eregOfRexRM(pfx, modrm);
16933 assign( srcVec, getXMMReg(rE) );
16935 DIP( "vpmov%cxbd %s,%s\n", how, nameXMMReg(rE), nameYMMReg(rG) );
16979 UInt rE = eregOfRexRM(pfx, modrm);
16980 assign( srcBytes, getXMMRegLane16( rE, 0 ) );
16982 DIP( "%spmovsxbq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
17011 UInt rE = eregOfRexRM(pfx, modrm);
17012 assign( srcBytes, getXMMRegLane32( rE, 0 ) );
17014 DIP( "vpmovsxbq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
17058 UInt rE = eregOfRexRM(pfx, modrm);
17059 assign( srcVec, getXMMReg(rE) );
17061 DIP( "%spmovzxbq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
17096 UInt rE = eregOfRexRM(pfx, modrm);
17097 assign( srcVec, getXMMReg(rE) );
17099 DIP( "vpmovzxbq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG) );
17144 UInt rE = eregOfRexRM(pfx,modrm);
17145 assign( sV, getXMMReg(rE) );
17147 DIP("%sphminposuw %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
17483 UInt rE = eregOfRexRM(pfx,modrm);
17484 assign( sV, getXMMReg(rE) );
17486 DIP("pmuldq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
17897 UInt rE = eregOfRexRM(pfx,modrm);
17898 putIReg32( rE, unop(Iop_16Uto32, mkexpr(d16)) );
17901 nameXMMReg( rG ), nameIReg32( rE ) );
18597 UInt rE = eregOfRexRM(pfx,modrm);
18598 putIReg32( rE, mkexpr(src_dword) );
18601 nameXMMReg( rG ), nameIReg32( rE ) );
19008 UInt rE = eregOfRexRM(pfx,modrm);
19010 assign( new8, unop(Iop_32to8, getIReg32(rE)) );
19013 nameIReg32(rE), nameXMMReg(rG) );
19042 UInt rE = eregOfRexRM(pfx, modrm);
19044 assign( vE, getXMMReg(rE) );
19051 imm8, nameXMMReg(rE), nameXMMReg(rG) );
19080 UInt rE = eregOfRexRM(pfx,modrm);
19082 assign( src_u32, getIReg32( rE ) );
19085 imm8_10, nameIReg32(rE), nameXMMReg(rG) );
19111 UInt rE = eregOfRexRM(pfx,modrm);
19113 assign( src_u64, getIReg64( rE ) );
19116 imm8_0, nameIReg64(rE), nameXMMReg(rG) );
19145 UInt rE = eregOfRexRM(pfx, modrm);
19147 assign( src_vec, getXMMReg(rE) );
19150 imm8, nameXMMReg(rE), nameXMMReg(rG) );
19178 UInt rE = eregOfRexRM(pfx, modrm);
19180 assign( src_vec, getXMMReg(rE) );
19183 imm8, nameXMMReg(rE), nameXMMReg(rG) );
19213 UInt rE = eregOfRexRM(pfx, modrm);
19216 assign( src_vec, getXMMReg(rE) );
19219 nameXMMReg(rE), nameXMMReg(rG) );
19251 UInt rE = eregOfRexRM(pfx, modrm);
19253 assign( svec, getXMMReg(rE) );
19256 nameXMMReg(rE), nameXMMReg(rG) );
19990 /* If REX.B is 1, we're not exchanging rAX with itself */
20468 /* Same comments re operand size as for LEAVE below apply.
20647 /* This is correct, both for 32- and 64-bit versions. If we're
21085 /* declare we're writing memory */
21734 unchanged. If the DCAS fails then we're putting into
21744 expdHi64:expdLo64, even if we're doing a cmpxchg8b. */
22219 UInt rE = eregOfRexRM(pfx,modrm);
22220 assign( amt, getXMMRegLane64(rE, 0) );
22221 DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
22293 UInt rE = eregOfRexRM(pfx,modrm);
22294 assign( amt, getXMMRegLane64(rE, 0) );
22295 DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
22367 UInt rE = eregOfRexRM(pfx,modrm);
22368 assign( amt, isYMM ? getYMMReg(rE) : getXMMReg(rE) );
22370 DIP("%s %s,%s,%s\n", opname, nameYMMReg(rE),
22373 DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
22596 UInt rE = eregOfRexRM(pfx,rm);
22597 putXMMReg( rG, binop(op, vpart, getXMMReg(rE)) );
22599 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
22641 UInt rE = eregOfRexRM(pfx,rm);
22642 assign(e64, getXMMRegLane64(rE, 0));
22644 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
22688 UInt rE = eregOfRexRM(pfx,rm);
22689 assign(e32, getXMMRegLane32(rE, 0));
22691 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
22733 UInt rE = eregOfRexRM(pfx,rm);
22734 putXMMReg( rG, binop(op, vpart, getXMMReg(rE)) );
22736 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
22802 UInt rE = eregOfRexRM(pfx,rm);
22803 assign(argR, getXMMReg(rE));
22807 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
22917 UInt rE = eregOfRexRM(pfx,rm);
22918 assign(argR, getYMMReg(rE));
22922 nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
22970 UInt rE = eregOfRexRM(pfx,rm);
22971 assign(arg, getXMMReg(rE));
22973 DIP("%s %s,%s\n", opname, nameXMMReg(rE), nameXMMReg(rG));
23001 UInt rE = eregOfRexRM(pfx,rm);
23002 assign(arg, getXMMReg(rE));
23004 DIP("%s %s,%s\n", opname, nameXMMReg(rE), nameXMMReg(rG));
23145 UInt rE = eregOfRexRM(pfx,rm);
23146 assign(arg, getYMMReg(rE));
23148 DIP("%s %s,%s\n", opname, nameYMMReg(rE), nameYMMReg(rG));
23176 UInt rE = eregOfRexRM(pfx,rm);
23177 assign(arg, getYMMReg(rE));
23179 DIP("%s %s,%s\n", opname, nameYMMReg(rE), nameYMMReg(rG));
23204 UInt rE = eregOfRexRM(pfx,modrm);
23205 assign( sV, getXMMReg(rE) );
23207 DIP("vcvtdq2pd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
23241 UInt rE = eregOfRexRM(pfx,modrm);
23242 assign( argV, getYMMReg(rE) );
23244 DIP("vcvtpd2psy %s,%s\n", nameYMMReg(rE), nameXMMReg(rG));
23400 UInt rE = eregOfRexRM(pfx, modrm);
23404 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23408 getXMMRegLane64(rE, 0)));
23435 UInt rE = eregOfRexRM(pfx, modrm);
23439 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23445 getXMMRegLane32(rE, 0)) ) );
23455 UInt rE = eregOfRexRM(pfx,modrm);
23456 putYMMRegLoAndZU( rG, getXMMReg( rE ));
23457 DIP("vmovupd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
23472 UInt rE = eregOfRexRM(pfx,modrm);
23473 putYMMReg( rG, getYMMReg( rE ));
23474 DIP("vmovupd %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
23489 UInt rE = eregOfRexRM(pfx,modrm);
23490 putYMMRegLoAndZU( rG, getXMMReg( rE ));
23491 DIP("vmovups %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
23506 UInt rE = eregOfRexRM(pfx,modrm);
23507 putYMMReg( rG, getYMMReg( rE ));
23508 DIP("vmovups %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
23538 UInt rE = eregOfRexRM(pfx, modrm);
23542 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23546 getXMMRegLane64(rE, 0)));
23568 UInt rE = eregOfRexRM(pfx, modrm);
23572 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23578 getXMMRegLane32(rE, 0)) ) );
23588 UInt rE = eregOfRexRM(pfx,modrm);
23589 putYMMRegLoAndZU( rE, getXMMReg(rG) );
23590 DIP("vmovupd %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
23605 UInt rE = eregOfRexRM(pfx,modrm);
23606 putYMMReg( rE, getYMMReg(rG) );
23607 DIP("vmovupd %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
23622 UInt rE = eregOfRexRM(pfx,modrm);
23623 putYMMRegLoAndZU( rE, getXMMReg(rG) );
23624 DIP("vmovups %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
23639 UInt rE = eregOfRexRM(pfx,modrm);
23640 putYMMReg( rE, getYMMReg(rG) );
23641 DIP("vmovups %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
23670 UInt rE = eregOfRexRM(pfx, modrm);
23674 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23678 getXMMRegLane64(rE, 1)));
23747 UInt rE = eregOfRexRM(pfx,modrm);
23748 assign( eV, getXMMReg(rE) );
23751 nameXMMReg(rE), nameXMMReg(rG));
23775 UInt rE = eregOfRexRM(pfx,modrm);
23776 assign( eV, getYMMReg(rE) );
23779 nameYMMReg(rE), nameYMMReg(rG));
23803 UInt rE = eregOfRexRM(pfx,modrm);
23804 assign( eV, getXMMReg(rE) );
23807 nameXMMReg(rE), nameXMMReg(rG));
23831 UInt rE = eregOfRexRM(pfx,modrm);
23832 assign( eV, getYMMReg(rE) );
23835 nameYMMReg(rE), nameYMMReg(rG));
23857 UInt rE = eregOfRexRM(pfx, modrm);
23861 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
23864 getXMMRegLane64(rE, 0),
23928 UInt rE = eregOfRexRM(pfx,modrm);
23929 putYMMRegLoAndZU( rG, getXMMReg( rE ));
23930 DIP("vmovapd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
23946 UInt rE = eregOfRexRM(pfx,modrm);
23947 putYMMReg( rG, getYMMReg( rE ));
23948 DIP("vmovapd %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
23964 UInt rE = eregOfRexRM(pfx,modrm);
23965 putYMMRegLoAndZU( rG, getXMMReg( rE ));
23966 DIP("vmovaps %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
23982 UInt rE = eregOfRexRM(pfx,modrm);
23983 putYMMReg( rG, getYMMReg( rE ));
23984 DIP("vmovaps %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
24003 UInt rE = eregOfRexRM(pfx,modrm);
24004 putYMMRegLoAndZU( rE, getXMMReg(rG) );
24005 DIP("vmovapd %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
24021 UInt rE = eregOfRexRM(pfx,modrm);
24022 putYMMReg( rE, getYMMReg(rG) );
24023 DIP("vmovapd %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
24039 UInt rE = eregOfRexRM(pfx,modrm);
24040 putYMMRegLoAndZU( rE, getXMMReg(rG) );
24041 DIP("vmovaps %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
24058 UInt rE = eregOfRexRM(pfx,modrm);
24059 putYMMReg( rE, getYMMReg(rG) );
24060 DIP("vmovaps %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
25570 UInt rE = eregOfRexRM(pfx,modrm);
25571 assign( sV, getXMMReg(rE) );
25572 DIP("vh%spd %s,%s,%s\n", str, nameXMMReg(rE),
25600 UInt rE = eregOfRexRM(pfx,modrm);
25601 assign( sV, getYMMReg(rE) );
25602 DIP("vh%spd %s,%s,%s\n", str, nameYMMReg(rE),
25632 UInt rE = eregOfRexRM(pfx,modrm);
25633 assign( sV, getXMMReg(rE) );
25634 DIP("vh%spd %s,%s,%s\n", str, nameXMMReg(rE),
25662 UInt rE = eregOfRexRM(pfx,modrm);
25663 assign( sV, getYMMReg(rE) );
25664 DIP("vh%spd %s,%s,%s\n", str, nameYMMReg(rE),
25697 UInt rE = eregOfRexRM(pfx,modrm);
25698 putXMMRegLane64( rG, 0, getXMMRegLane64( rE, 0 ));
25699 DIP("vmovq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
25720 UInt rE = eregOfRexRM(pfx,modrm);
25721 DIP("vmovq %s,%s\n", nameXMMReg(rG), nameIReg64(rE));
25722 putIReg64(rE, getXMMRegLane64(rG, 0));
25739 UInt rE = eregOfRexRM(pfx,modrm);
25740 DIP("vmovd %s,%s\n", nameXMMReg(rG), nameIReg32(rE));
25741 putIReg32(rE, getXMMRegLane32(rG, 0));
25946 UInt rE = eregOfRexRM(pfx,modrm);
25947 assign( eV, getXMMReg(rE) );
25951 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
25976 UInt rE = eregOfRexRM(pfx,modrm);
25977 assign( eV, getYMMReg(rE) );
25981 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
26006 UInt rE = eregOfRexRM(pfx,modrm);
26007 assign( eV, getXMMReg(rE) );
26011 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
26036 UInt rE = eregOfRexRM(pfx,modrm);
26037 assign( eV, getYMMReg(rE) );
26041 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
26316 /* VPANDN r/m, rV, r ::: r = rV & ~r/m (is that correct, re the ~ ?) */
26324 /* VPANDN r/m, rV, r ::: r = rV & ~r/m (is that correct, re the ~ ?) */
27096 UInt rE = eregOfRexRM(pfx, modrm);
27100 ? getXMMRegLane64F(rE, 0) : getXMMRegLane32F(rE, 0) );
27102 assign( vY, vty == Ity_V256 ? getYMMReg(rE) : getXMMReg(rE) );
27105 name, order, suffix, nameYMMReg(rE), nameYMMReg(rV),
27109 name, order, suffix, nameXMMReg(rE), nameXMMReg(rV),
27481 UInt rE = eregOfRexRM(pfx,modrm);
27482 assign( sV, getXMMReg(rE) );
27484 DIP("vpsign%c %s,%s,%s\n", ch, nameXMMReg(rE),
27532 UInt rE = eregOfRexRM(pfx,modrm);
27533 assign( sV, getYMMReg(rE) );
27535 DIP("vpsign%c %s,%s,%s\n", ch, nameYMMReg(rE),
27580 UInt rE = eregOfRexRM(pfx,modrm);
27581 assign( sV, getXMMReg(rE) );
27583 DIP("vpmulhrsw %s,%s,%s\n", nameXMMReg(rE),
27619 UInt rE = eregOfRexRM(pfx,modrm);
27620 assign( sV, getYMMReg(rE) );
27622 DIP("vpmulhrsw %s,%s,%s\n", nameYMMReg(rE),
27660 UInt rE = eregOfRexRM(pfx, modrm);
27663 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
27664 assign(ctrlV, getXMMReg(rE));
27687 UInt rE = eregOfRexRM(pfx, modrm);
27690 nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
27691 assign(ctrlV, getYMMReg(rE));
27717 UInt rE = eregOfRexRM(pfx, modrm);
27720 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
27721 assign(ctrlV, getXMMReg(rE));
27744 UInt rE = eregOfRexRM(pfx, modrm);
27747 nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
27748 assign(ctrlV, getYMMReg(rE));
27856 UInt rE = eregOfRexRM(pfx, modrm);
27857 DIP("vbroadcastss %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
27859 assign(t32, getXMMRegLane32(rE, 0));
27873 UInt rE = eregOfRexRM(pfx, modrm);
27874 DIP("vbroadcastss %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
27876 assign(t32, getXMMRegLane32(rE, 0));
27910 UInt rE = eregOfRexRM(pfx, modrm);
27911 DIP("vbroadcastsd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
27913 assign(t64, getXMMRegLane64(rE, 0));
28532 UInt rE = eregOfRexRM(pfx, modrm);
28534 DIP("vpbroadcastd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
28535 assign(t32, getXMMRegLane32(rE, 0));
28555 UInt rE = eregOfRexRM(pfx, modrm);
28557 DIP("vpbroadcastd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
28558 assign(t32, getXMMRegLane32(rE, 0));
28582 UInt rE = eregOfRexRM(pfx, modrm);
28584 DIP("vpbroadcastq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
28585 assign(t64, getXMMRegLane64(rE, 0));
28603 UInt rE = eregOfRexRM(pfx, modrm);
28605 DIP("vpbroadcastq %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
28606 assign(t64, getXMMRegLane64(rE, 0));
28645 UInt rE = eregOfRexRM(pfx, modrm);
28646 DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
28647 assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
28671 UInt rE = eregOfRexRM(pfx, modrm);
28672 DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
28673 assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
28701 UInt rE = eregOfRexRM(pfx, modrm);
28702 DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
28703 assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
28725 UInt rE = eregOfRexRM(pfx, modrm);
28726 DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
28727 assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
29547 UInt rE = eregOfRexRM(pfx, modrm);
29551 name, imm8, nameYMMReg(rE), nameYMMReg(rG));
29552 assign(sV, getYMMReg(rE));
29590 UInt rE = eregOfRexRM(pfx, modrm);
29594 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
29595 assign(dV, getXMMReg(rE));
29630 UInt rE = eregOfRexRM(pfx, modrm);
29634 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
29635 assign(dV, getYMMReg(rE));
29668 UInt rE = eregOfRexRM(pfx, modrm);
29672 imm8, nameYMMReg(rE), nameYMMReg(rG));
29673 assign(sV, getYMMReg(rE));
29698 UInt rE = eregOfRexRM(pfx, modrm);
29702 imm8, nameXMMReg(rE), nameXMMReg(rG));
29703 assign(sV, getXMMReg(rE));
29726 UInt rE = eregOfRexRM(pfx, modrm);
29730 imm8, nameXMMReg(rE), nameXMMReg(rG));
29731 assign(sV, getXMMReg(rE));
29759 UInt rE = eregOfRexRM(pfx, modrm);
29763 imm8, nameYMMReg(rE), nameYMMReg(rG));
29764 assign(sV, getYMMReg(rE));
29803 UInt rE = eregOfRexRM(pfx, modrm);
29807 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
29808 assign(s10, getYMMRegLane128(rE, 0));
29809 assign(s11, getYMMRegLane128(rE, 1));
29851 UInt rE = eregOfRexRM(pfx, modrm);
29852 assign( src, getXMMReg( rE ) );
29856 DIP( "vroundps $%d,%s,%s\n", imm, nameXMMReg(rE), nameXMMReg(rG) );
29903 UInt rE = eregOfRexRM(pfx, modrm);
29904 assign( src, getYMMReg( rE ) );
29908 DIP( "vroundps $%d,%s,%s\n", imm, nameYMMReg(rE), nameYMMReg(rG) );
29954 UInt rE = eregOfRexRM(pfx, modrm);
29955 assign( src, getXMMReg( rE ) );
29959 DIP( "vroundpd $%d,%s,%s\n", imm, nameXMMReg(rE), nameXMMReg(rG) );
30000 UInt rE = eregOfRexRM(pfx, modrm);
30001 assign( src, getYMMReg( rE ) );
30005 DIP( "vroundpd $%d,%s,%s\n", imm, nameYMMReg(rE), nameYMMReg(rG) );
30048 UInt rE = eregOfRexRM(pfx, modrm);
30050 isD ? getXMMRegLane64F(rE, 0) : getXMMRegLane32F(rE, 0) );
30056 imm, nameXMMReg( rE ), nameXMMReg( rV ), nameXMMReg( rG ) );
30102 UInt rE = eregOfRexRM(pfx, modrm);
30106 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30107 assign(sE, getYMMReg(rE));
30133 UInt rE = eregOfRexRM(pfx, modrm);
30137 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
30138 assign(sE, getXMMReg(rE));
30167 UInt rE = eregOfRexRM(pfx, modrm);
30171 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30172 assign(sE, getYMMReg(rE));
30198 UInt rE = eregOfRexRM(pfx, modrm);
30202 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
30203 assign(sE, getXMMReg(rE));
30232 UInt rE = eregOfRexRM(pfx, modrm);
30236 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
30237 assign(sE, getXMMReg(rE));
30265 UInt rE = eregOfRexRM(pfx, modrm);
30269 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30270 assign(sE, getYMMReg(rE));
30304 UInt rE = eregOfRexRM(pfx, modrm);
30305 assign( sV, getXMMReg(rE) );
30308 rE),
30339 UInt rE = eregOfRexRM(pfx, modrm);
30340 assign( sV, getYMMReg(rE) );
30343 DIP("vpalignr $%d,%s,%s,%s\n", imm8, nameYMMReg(rE),
30420 UInt rE = eregOfRexRM(pfx, modrm);
30422 assign(t128, getXMMReg(rE));
30425 ib, nameXMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30487 UInt rE = eregOfRexRM(pfx,modrm);
30489 assign( src_u8, unop(Iop_32to8, getIReg32( rE )) );
30492 imm8, nameIReg32(rE), nameXMMReg(rV), nameXMMReg(rG) );
30523 UInt rE = eregOfRexRM(pfx, modrm);
30525 assign( vE, getXMMReg(rE) );
30532 imm8, nameXMMReg(rE), nameXMMReg(rG) );
30562 UInt rE = eregOfRexRM(pfx,modrm);
30564 assign( src_u32, getIReg32( rE ) );
30567 imm8_10, nameIReg32(rE), nameXMMReg(rV), nameXMMReg(rG) );
30594 UInt rE = eregOfRexRM(pfx,modrm);
30596 assign( src_u64, getIReg64( rE ) );
30599 imm8_0, nameIReg64(rE), nameXMMReg(rV), nameXMMReg(rG) );
30630 UInt rE = eregOfRexRM(pfx, modrm);
30632 assign(t128, getXMMReg(rE));
30635 ib, nameXMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30695 UInt rE = eregOfRexRM(pfx,modrm);
30697 assign( dst_vec, getXMMReg( rE ) );
30700 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
30725 UInt rE = eregOfRexRM(pfx,modrm);
30727 assign( dst_vec, getYMMReg( rE ) );
30730 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG) );
30763 UInt rE = eregOfRexRM(pfx,modrm);
30765 assign( dst_vec, getXMMReg( rE ) );
30768 imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
30801 UInt rE = eregOfRexRM(pfx, modrm);
30804 assign( src_vec, getXMMReg(rE) );
30807 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
30838 UInt rE = eregOfRexRM(pfx, modrm);
30841 assign( src_vec, getYMMReg(rE) );
30844 nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG) );
30883 UInt rE = eregOfRexRM(pfx, modrm);
30885 assign( sV, getXMMReg(rE) );
30888 nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
30920 UInt rE = eregOfRexRM(pfx, modrm);
30924 imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
30925 assign(s10, getYMMRegLane128(rE, 0));
30926 assign(s11, getYMMRegLane128(rE, 1));
31209 // Invalidate the current insn. The reason is that the IRop we're
31372 /* Eat up opcode escape bytes, until we're really looking at the
31388 /* So now we're really really looking at the primary opcode
31799 /* inconsistency detected. re-disassemble the instruction so as
