Lines Matching defs:Ta
3169 IRTemp ta = newTemp(Ity_I64);
3170 assign(ta, binop(Iop_Add64, getIReg64orSP(nn), mkU64(offs)));
3174 putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta)));
3176 gen_narrowing_store(szB, ta, getIReg64orZR(tt));
3227 // Compute the transfer address TA and the writeback address WA.
3331 // Compute the transfer address TA and the writeback address WA.
3767 // Compute the transfer address TA and the writeback address WA.
6603 001 01110 sz 1 m 110000 n d UMULL Vd.Ta, Vn.Tb, Vm.Tb
6930 0q0 011110 immh immb 100001 n d SHRN Vd.Tb, Vn.Ta, #sh
6932 where Ta,Tb,sh
6950 const HChar* ta = "??";
6994 0q0 011110 immh immb 101001 n d SSHLL Vd.Ta, Vn.Tb, #sh
6995 0q1 011110 immh immb 101001 n d USHLL Vd.Ta, Vn.Tb, #sh
6996 where Ta,Tb,sh
7016 const HChar* ta = "??";
7026 ta = "2d";
7035 ta = "4s";
7044 ta = "8h";
7058 nameQReg128(dd), ta, nameQReg128(nn), tb, sh);
7065 /* 31 28 23 21 15 9 4 XTN{,2} Vd.Tb, Vn.Ta
7077 const HChar* ta = NULL;
7079 case 0: tb = "8b"; ta = "8h"; op = Iop_NarrowUn16to8x8; break;
7080 case 1: tb = "16b"; ta = "8h"; op = Iop_NarrowUn16to8x8; break;
7081 case 2: tb = "4h"; ta = "4s"; op = Iop_NarrowUn32to16x4; break;
7082 case 3: tb = "8h"; ta = "4s"; op = Iop_NarrowUn32to16x4; break;
7083 case 4: tb = "2s"; ta = "2d"; op = Iop_NarrowUn64to32x2; break;
7084 case 5: tb = "4s"; ta = "2d"; op = Iop_NarrowUn64to32x2; break;
7095 nameQReg128(dd), tb, nameQReg128(nn), ta);
7513 0q0 01110 000 m 0 len 000 n d TBL Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta
7514 0q0 01110 000 m 0 len 100 n d TBX Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta
7515 where Ta = 16b(q=1) or 8b(q=0)
7542 const HChar* Ta = isQ ? "16b" : "8b";
7545 nm, nameQReg128(dd), Ta, nn, (nn + len) % 32, nameQReg128(mm), Ta);
