Lines Matching defs:rM
2300 x 0 0 01011 sh 0 Rm imm6 Rn Rd ADD Rd,Rn, sh(Rm,imm6)
2301 x 0 1 01011 sh 0 Rm imm6 Rn Rd ADDS Rd,Rn, sh(Rm,imm6)
2302 x 1 0 01011 sh 0 Rm imm6 Rn Rd SUB Rd,Rn, sh(Rm,imm6)
2303 x 1 1 01011 sh 0 Rm imm6 Rn Rd SUBS Rd,Rn, sh(Rm,imm6)
2310 UInt rM = INSN(20,16);
2322 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False);
2333 nameIRegOrZR(is64, rM), nameSH(sh), imm6);
2343 x 0 0 11010 00 0 Rm 000000 Rn Rd ADC Rd,Rn,Rm
2344 x 0 1 11010 00 0 Rm 000000 Rn Rd ADCS Rd,Rn,Rm
2345 x 1 0 11010 00 0 Rm 000000 Rn Rd SBC Rd,Rn,Rm
2346 x 1 1 11010 00 0 Rm 000000 Rn Rd SBCS Rd,Rn,Rm
2353 UInt rM = INSN(20,16);
2369 assign(argR, getIRegOrZR(is64, rM));
2396 nameIRegOrZR(is64, rM));
2410 x 00 01010 sh N Rm imm6 Rn Rd AND Rd,Rn, inv?(sh(Rm,imm6))
2411 x 01 01010 sh N Rm imm6 Rn Rd ORR Rd,Rn, inv?(sh(Rm,imm6))
2412 x 10 01010 sh N Rm imm6 Rn Rd EOR Rd,Rn, inv?(sh(Rm,imm6))
2413 x 11 01010 sh N Rm imm6 Rn Rd ANDS Rd,Rn, inv?(sh(Rm,imm6))
2420 UInt rM = INSN(20,16);
2431 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, bN == 1);
2453 nameIRegOrZR(is64, rM));
2457 nameIRegOrZR(is64, rM), nameSH(sh), imm6);
2465 10011011 1 10 Rm 011111 Rn Rd UMULH Xd,Xn,Xm
2466 10011011 0 10 Rm 011111 Rn Rd SMULH Xd,Xn,Xm
2485 sf 00 11011 000 m 0 a n r MADD Rd,Rn,Rm,Ra d = a+m*n
2486 sf 00 11011 000 m 1 a n r MADD Rd,Rn,Rm,Ra d = a-m*n
2517 sf 00 1101 0100 mm cond 00 nn dd CSEL Rd,Rn,Rm
2518 sf 00 1101 0100 mm cond 01 nn dd CSINC Rd,Rn,Rm
2519 sf 10 1101 0100 mm cond 00 nn dd CSINV Rd,Rn,Rm
2520 sf 10 1101 0100 mm cond 01 nn dd CSNEG Rd,Rn,Rm
2521 In all cases, the operation is: Rd = if cond then Rn else OP(Rm)
2565 100 01011 00 1 m opt imm3 n d ADD Xd|SP, Xn|SP, Rm ext&lsld
2568 101 01011 00 1 m opt imm3 n d ADDS Xd, Xn|SP, Rm ext&lsld
2571 110 01011 00 1 m opt imm3 n d SUB Xd|SP, Xn|SP, Rm ext&lsld
2574 111 01011 00 1 m opt imm3 n d SUBS Xd, Xn|SP, Rm ext&lsld
2724 sf 1 111010010 Rm cond 00 Rn 0 nzcv CCMP Rn, Rm, #nzcv, cond
2725 sf 0 111010010 Rm cond 00 Rn 0 nzcv CCMN Rn, Rm, #nzcv, cond
2727 (CCMP) flags = if cond then flags-after-sub(Rn,Rm) else nzcv
2728 (CCMN) flags = if cond then flags-after-add(Rn,Rm) else nzcv
2866 sf 00 1101 0110 m 0010 00 n d LSLV Rd,Rn,Rm
2867 sf 00 1101 0110 m 0010 01 n d LSRV Rd,Rn,Rm
2868 sf 00 1101 0110 m 0010 10 n d ASRV Rd,Rn,Rm
2905 sf 00 1101 0110 m 00001 1 n d SDIV Rd,Rn,Rm
2906 sf 00 1101 0110 m 00001 0 n d UDIV Rd,Rn,Rm
2989 Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of
3446 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R<m>{ext/sh}]
3447 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R<m>{ext/sh}]
3448 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R<m>{ext/sh}]
3449 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R<m>{ext/sh}]
3451 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R<m>{ext/sh}]
3452 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R<m>{ext/sh}]
3453 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R<m>{ext/sh}]
3454 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R<m>{ext/sh}]
3861 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R<m>{ext/sh}]
3862 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R<m>{ext/sh}]
3863 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R<m>{ext/sh}]
3864 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R<m>{ext/sh}]
3865 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R<m>{ext/sh}]
3867 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R<m>{ext/sh}]
3868 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R<m>{ext/sh}]
3869 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R<m>{ext/sh}]
3870 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R<m>{ext/sh}]
3871 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R<m>{ext/sh}]
3935 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R<m>{ext/sh}]
3937 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R<m>{ext/sh}]
3938 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R<m>{ext/sh}]
3940 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R<m>{ext/sh}]
3941 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R<m>{ext/sh}]
4938 /* begin FIXME -- rm temp scaffolding */
4956 /* end FIXME -- rm temp scaffolding */
5494 UInt rm = INSN(20,19); // rmode
5500 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1))
5503 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0))
5507 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1))
5510 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0))
5513 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1))
5516 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0))
5885 IRExpr* rm = mkexpr(mk_get_IR_rounding_mode());
5886 IRExpr* eNxM = triop(opMUL, rm, eN, eM);
5888 case 0: assign(res, triop(opADD, rm, eA, eNxM)); break;
5889 case 1: assign(res, triop(opSUB, rm, eA, eNxM)); break;
5890 case 2: assign(res, unop(opNEG, triop(opADD, rm, eA, eNxM))); break;
5891 case 3: assign(res, unop(opNEG, triop(opSUB, rm, eA, eNxM))); break;
5919 UInt rm = INSN(20,19);
5926 switch (rm) {
6030 rm
6032 rm (17:15) encodings:
6045 UInt rm = INSN(17,15);
6051 switch (rm) {
6163 IRTemp rm = mk_get_IR_rounding_mode();
6168 binop(op, mkexpr(rm), getQRegLane(nn, i, tyI)));
6222 IRTemp rm = mk_get_IR_rounding_mode();
6225 assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
6237 IRTemp rm = mk_get_IR_rounding_mode();
6242 mkexpr(rm), getQReg128(nn), getQReg128(mm)));
6244 mkexpr(rm), getQReg128(dd), mkexpr(t1)));
6254 IRTemp rm = mk_get_IR_rounding_mode();
6259 mkexpr(rm), getQReg128(nn), getQReg128(mm)));
6364 IRTemp rm = mk_get_IR_rounding_mode();
6367 putQRegLane(dd, 2 * bQ + 0, binop(Iop_F64toF32, mkexpr(rm), srcLo));
6368 putQRegLane(dd, 2 * bQ + 1, binop(Iop_F64toF32, mkexpr(rm), srcHi));
