Lines Matching defs:rN
1979 sf op 100100 N immr imms Rn Rd
1980 op=00: AND Rd|SP, Rn, #imm
1981 op=01: ORR Rd|SP, Rn, #imm
1982 op=10: EOR Rd|SP, Rn, #imm
1983 op=11: ANDS Rd|ZR, Rn, #imm
2300 x 0 0 01011 sh 0 Rm imm6 Rn Rd ADD Rd,Rn, sh(Rm,imm6)
2301 x 0 1 01011 sh 0 Rm imm6 Rn Rd ADDS Rd,Rn, sh(Rm,imm6)
2302 x 1 0 01011 sh 0 Rm imm6 Rn Rd SUB Rd,Rn, sh(Rm,imm6)
2303 x 1 1 01011 sh 0 Rm imm6 Rn Rd SUBS Rd,Rn, sh(Rm,imm6)
2312 UInt rN = INSN(9,5);
2321 assign(argL, getIRegOrZR(is64, rN));
2332 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN),
2343 x 0 0 11010 00 0 Rm 000000 Rn Rd ADC Rd,Rn,Rm
2344 x 0 1 11010 00 0 Rm 000000 Rn Rd ADCS Rd,Rn,Rm
2345 x 1 0 11010 00 0 Rm 000000 Rn Rd SBC Rd,Rn,Rm
2346 x 1 1 11010 00 0 Rm 000000 Rn Rd SBCS Rd,Rn,Rm
2354 UInt rN = INSN(9,5);
2367 assign(argL, getIRegOrZR(is64, rN));
2395 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN),
2410 x 00 01010 sh N Rm imm6 Rn Rd AND Rd,Rn, inv?(sh(Rm,imm6))
2411 x 01 01010 sh N Rm imm6 Rn Rd ORR Rd,Rn, inv?(sh(Rm,imm6))
2412 x 10 01010 sh N Rm imm6 Rn Rd EOR Rd,Rn, inv?(sh(Rm,imm6))
2413 x 11 01010 sh N Rm imm6 Rn Rd ANDS Rd,Rn, inv?(sh(Rm,imm6))
2422 UInt rN = INSN(9,5);
2430 assign(argL, getIRegOrZR(is64, rN));
2451 if (rN == 31/*zr*/ && sh == 0/*LSL*/ && imm6 == 0 && bN == 0) {
2456 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN),
2465 10011011 1 10 Rm 011111 Rn Rd UMULH Xd,Xn,Xm
2466 10011011 0 10 Rm 011111 Rn Rd SMULH Xd,Xn,Xm
2485 sf 00 11011 000 m 0 a n r MADD Rd,Rn,Rm,Ra d = a+m*n
2486 sf 00 11011 000 m 1 a n r MADD Rd,Rn,Rm,Ra d = a-m*n
2517 sf 00 1101 0100 mm cond 00 nn dd CSEL Rd,Rn,Rm
2518 sf 00 1101 0100 mm cond 01 nn dd CSINC Rd,Rn,Rm
2519 sf 10 1101 0100 mm cond 00 nn dd CSINV Rd,Rn,Rm
2520 sf 10 1101 0100 mm cond 01 nn dd CSNEG Rd,Rn,Rm
2521 In all cases, the operation is: Rd = if cond then Rn else OP(Rm)
2684 sf 1 111010010 imm5 cond 10 Rn 0 nzcv CCMP Rn, #imm5, #nzcv, cond
2685 sf 0 111010010 imm5 cond 10 Rn 0 nzcv CCMN Rn, #imm5, #nzcv, cond
2688 (CCMP) flags = if cond then flags-after-sub(Rn,imm5) else nzcv
2689 (CCMN) flags = if cond then flags-after-add(Rn,imm5) else nzcv
2724 sf 1 111010010 Rm cond 00 Rn 0 nzcv CCMP Rn, Rm, #nzcv, cond
2725 sf 0 111010010 Rm cond 00 Rn 0 nzcv CCMN Rn, Rm, #nzcv, cond
2727 (CCMP) flags = if cond then flags-after-sub(Rn,Rm) else nzcv
2728 (CCMN) flags = if cond then flags-after-add(Rn,Rm) else nzcv
2832 sf 10 1101 0110 00000 00010 0 n d CLZ Rd, Rn
2833 sf 10 1101 0110 00000 00010 1 n d CLS Rd, Rn
2866 sf 00 1101 0110 m 0010 00 n d LSLV Rd,Rn,Rm
2867 sf 00 1101 0110 m 0010 01 n d LSRV Rd,Rn,Rm
2868 sf 00 1101 0110 m 0010 10 n d ASRV Rd,Rn,Rm
2905 sf 00 1101 0110 m 00001 1 n d SDIV Rd,Rn,Rm
2906 sf 00 1101 0110 m 00001 0 n d UDIV Rd,Rn,Rm
2989 Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of
3190 (at-Rn-then-Rn=EA) | | |
3191 sz 111 00000 0 imm9 01 Rn Rt STR Rt, [Xn|SP], #simm9
3192 sz 111 00001 0 imm9 01 Rn Rt LDR Rt, [Xn|SP], #simm9
3194 (at-EA-then-Rn=EA)
3195 sz 111 00000 0 imm9 11 Rn Rt STR Rt, [Xn|SP, #simm9]!
3196 sz 111 00001 0 imm9 11 Rn Rt LDR Rt, [Xn|SP, #simm9]!
3199 sz 111 00000 0 imm9 00 Rn Rt STR Rt, [Xn|SP, #simm9]
3200 sz 111 00001 0 imm9 00 Rn Rt LDR Rt, [Xn|SP, #simm9]
3204 The case 'wback && Rn == Rt && Rt != 31' is disallowed. In the
3247 /* Normally rN would be updated after the transfer. However, in
3279 fmt_str = "%s %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
3282 fmt_str = "%s %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n";
3285 fmt_str = "%s %s, [%s, #%lld] (at-Rn)\n";
3304 (at-Rn-then-Rn=EA)
3305 x0 101 0001 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm
3307 (at-EA-then-Rn=EA)
3308 x0 101 0011 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]!
3311 x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]
3322 UInt rN = INSN(9,5);
3325 if ((bWBack && (rT1 == rN || rT2 == rN) && rN != 31)
3329 if (rN == 31) { /* FIXME generate stack alignment check */ }
3333 assign(tRN, getIReg64orSP(rN));
3351 /* Normally rN would be updated after the transfer. However, in
3364 && INSN(24,23) == BITS2(1,1) && rN == 31 && bL == 0;
3367 putIReg64orSP(rN, mkexpr(tEA));
3397 putIReg64orSP(rN, mkexpr(tEA));
3402 fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
3405 fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n";
3408 fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n";
3416 nameIReg64orSP(rN), simm7);
3446 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R<m>{ext/sh}]
3447 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R<m>{ext/sh}]
3448 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R<m>{ext/sh}]
3449 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R<m>{ext/sh}]
3451 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R<m>{ext/sh}]
3452 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R<m>{ext/sh}]
3453 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R<m>{ext/sh}]
3454 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R<m>{ext/sh}]
3573 /* (at-Rn-then-Rn=EA)
3579 (at-EA-then-Rn=EA)
3585 transfer-at-Rn when [11]==0, at EA when [11]==1
3742 (at-Rn-then-Rn=EA)
3745 (at-EA-then-Rn=EA)
3796 /* Normally rN would be updated after the transfer. However, in
3840 fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
3843 fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n";
3846 fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n";
3861 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R<m>{ext/sh}]
3862 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R<m>{ext/sh}]
3863 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R<m>{ext/sh}]
3864 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R<m>{ext/sh}]
3865 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R<m>{ext/sh}]
3867 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R<m>{ext/sh}]
3868 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R<m>{ext/sh}]
3869 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R<m>{ext/sh}]
3870 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R<m>{ext/sh}]
3871 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R<m>{ext/sh}]
3935 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R<m>{ext/sh}]
3937 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R<m>{ext/sh}]
3938 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R<m>{ext/sh}]
3940 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R<m>{ext/sh}]
3941 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R<m>{ext/sh}]
4029 (at-Rn-then-Rn=EA)
4036 (at-EA-then-Rn=EA)
4148 UInt rN = INSN(9,5);
4183 assign(tEA, getIReg64orSP(rN));
4184 if (rN == 31) { /* FIXME generate stack alignment check */ }
4192 vT, name, index, nameIReg64orSP(rN));
4215 UInt rN = INSN(9,5);
4220 assign(tEA, getIReg64orSP(rN));
4221 if (rN == 31) { /* FIXME generate stack alignment check */ }
4228 vT, name, nameIReg64orSP(rN));
4247 UInt rN = INSN(9,5);
4252 assign(tEA, getIReg64orSP(rN));
4253 if (rN == 31) { /* FIXME generate stack alignment check */ }
4261 vT, name, nameIReg64orSP(rN));
4282 UInt rN = INSN(9,5);
4287 assign(tEA, getIReg64orSP(rN));
4288 if (rN == 31) { /* FIXME generate stack alignment check */ }
4294 putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(16)));
4296 vT, name, nameIReg64orSP(rN));
4316 UInt rN = INSN(9,5);
4321 assign(tEA, getIReg64orSP(rN));
4322 if (rN == 31) { /* FIXME generate stack alignment check */ }
4329 putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(8)));
4331 vT, name, nameIReg64orSP(rN));
4349 UInt rN = INSN(9,5);
4354 assign(tEA, getIReg64orSP(rN));
4355 if (rN == 31) { /* FIXME generate stack alignment check */ }
4404 putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(32)));
4406 (vT+0) % 32, name, (vT+1) % 32, name, nameIReg64orSP(rN));
4420 UInt rN = INSN(9,5);
4424 assign(tEA, getIReg64orSP(rN));
4425 if (rN == 31) { /* FIXME generate stack alignment check */ }
4436 (vT+0) % 32, name, (vT+1) % 32, name, nameIReg64orSP(rN));
4606 1101011 00 10 11111 000000 nn 00000 RET Rn
4607 1101011 00 01 11111 000000 nn 00000 CALL Rn
4608 1101011 00 00 11111 000000 nn 00000 JMP Rn
7183 0q0 01110 000 imm5 000011 n d DUP Vd.T, Rn
7384 010 01110000 imm5 000111 n d INS Vd.Ts[ix], Rn
