Lines Matching full:szblg2
4451 UInt szBlg2 = INSN(31,30);
4458 vassert(szBlg2 < 4);
4459 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */
4474 DIP("ld%sx%s %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
4489 DIP("st%sx%s %s, %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
4505 UInt szBlg2 = INSN(31,30);
4510 vassert(szBlg2 < 4);
4511 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */
4524 DIP("lda%s %s, [%s]\n", suffix[szBlg2],
4530 DIP("stl%s %s, [%s]\n", suffix[szBlg2],
5137 Bool bitQ, UInt szBlg2 )
5140 vassert(szBlg2 < 4);
5143 switch ((szBlg2 << 1) | (bitQ ? 1 : 0)) {
5163 static Bool getLaneInfo_IMMH_IMMB ( /*OUT*/UInt* shift, /*OUT*/UInt* szBlg2,
5171 if (szBlg2) *szBlg2 = 3;
5176 if (szBlg2) *szBlg2 = 2;
5181 if (szBlg2) *szBlg2 = 1;
5186 if (szBlg2) *szBlg2 = 0;
6387 UInt szBlg2 = INSN(23,22);
6394 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
6400 vassert(szBlg2 < 4);
6401 IROp op = isSUB ? opsSUB[szBlg2] : opsADD[szBlg2];
6449 UInt szBlg2 = INSN(23,22);
6468 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
6469 vassert(szBlg2 < 4);
6473 opMUL = (bit29 == 1 && !isMLAS) ? opsPMUL[szBlg2]
6474 : opsMUL[szBlg2];
6475 opACC = isMLAS ? (bit29 == 1 ? opsSUB[szBlg2] : opsADD[szBlg2])
6509 UInt szBlg2 = INSN(23,22);
6516 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
6526 vassert(szBlg2 < 4);
6527 IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2])
6528 : (isU ? opMINU[szBlg2] : opMINS[szBlg2]);
6555 UInt szBlg2 = INSN(23,22);
6561 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2);
6563 if (szBlg2 == 3) ok = False;
6564 if (szBlg2 == 2 && !isQ) ok = False;
6575 vassert(szBlg2 < 3);
6576 IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2])
6577 : (isU ? opMINU[szBlg2] : opMINS[szBlg2]);
6594 IRType laneTy = tys[szBlg2];
6678 UInt szBlg2 = INSN(23,22);
6691 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2);
6708 vassert(ok && szBlg2 < 4);
6719 case 1: res = binop(opsEQ[szBlg2], argL, argR); break;
6720 case 2: res = unop(Iop_NotV128, binop(opsEQ[szBlg2],
6724 case 3: res = binop(opsGTU[szBlg2], argL, argR); break;
6725 case 4: res = binop(opsGTS[szBlg2], argL, argR); break;
6726 case 5: res = unop(Iop_NotV128, binop(opsGTU[szBlg2], argR, argL));
6728 case 6: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL));
6730 case 7: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL));
6732 case 8: res = binop(opsGTS[szBlg2], argL, argR); break;
6734 binop(opsGTS[szBlg2], argL, argR));
6736 case 10: res = binop(opsEQ[szBlg2], argL, argR); break;
6737 case 11: res = binop(opsGTS[szBlg2], argR, argL); break;
6827 UInt szBlg2 = 0;
6829 Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
6831 if (szBlg2 == 3) {
6875 UInt szBlg2 = 0;
6877 Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
6881 shift = (8 << szBlg2) - shift;
6883 if (ok && szBlg2 < 4 && shift >= 0 && shift <= (8 << szBlg2)
6884 && !(szBlg2 == 3/*64bit*/ && !isQ)) {
6888 case 1: op = opsSHRN[szBlg2]; nm = isInsert ? "sri" : "ushr"; break;
6889 case 2: op = opsSARN[szBlg2]; nm = "sshr"; break;
6890 case 3: op = opsSHLN[szBlg2]; nm = isInsert ? "sli" : "shl"; break;
6917 HChar laneCh = "bhsd"[szBlg2];
6918 UInt nLanes = (isQ ? 128 : 64) / (8 << szBlg2);
6953 UInt szBlg2 = 0;
6955 Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb);
6957 if (ok && shift >= 0 && szBlg2 < 3 && shift <= (8 << szBlg2)) {
6962 assign(src, binop(opsSHR[szBlg2], getQReg128(nn), mkU8(shift)));
6964 switch(szBlg2) {
6985 isQ ? "2" : "", nameQReg128(dd), isQ ? tbs_q1[szBlg2] : tbs_q0[szBlg2],
6986 nameQReg128(nn), tas[szBlg2], shift);
7490 UInt szBlg2 = INSN(23,22);
7495 Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 );
7500 vassert(szBlg2 < 4);
7501 assign(res, binop(opSUB[szBlg2], mkV128(0x0000), getQReg128(nn)));
