Lines Matching defs:cc
513 ARM64CondCode cc;
702 cc = ARM64cc_AL;
741 cc = ARM64cc_AL;
748 cc = iselCondCode( env, guard );
805 addInstr(env, ARM64Instr_Call( cc, target, nextArgReg, *retloc ));
1137 // https://github.com/armvixl/vixl/blob/master/src/a64/assembler-a64.cc
1458 ARM64CondCode cc = iselCondCode_wrk(env,e);
1459 vassert(cc != ARM64cc_NV);
1460 return cc;
1481 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
1482 if (cc == ARM64cc_AL || cc == ARM64cc_NV) {
1485 return 1 ^ cc;
2121 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
2122 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
2185 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
2186 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
2355 ARM64CondCode cc;
2359 cc = iselCondCode(env, e->Iex.ITE.cond);
2360 addInstr(env, ARM64Instr_CSel(dst, r1, r0, cc));
2672 //ZZ ARMCondCode cc;
2681 //ZZ cc = iselCondCode(env, e->Iex.ITE.cond);
2682 //ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstHi, ARMRI84_R(r0hi)));
2683 //ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstLo, ARMRI84_R(r0lo)));
5943 //ZZ ARMCondCode cc;
5948 //ZZ cc = iselCondCode(env, e->Iex.ITE.cond);
5949 //ZZ addInstr(env, ARMInstr_NCMovQ(cc ^ 1, dst, r0));
6125 //ZZ ARMCondCode cc = iselCondCode(env, e->Iex.ITE.cond);
6126 //ZZ addInstr(env, ARMInstr_VCMovD(cc ^ 1, dst, r0));
6297 //ZZ ARMCondCode cc;
6302 //ZZ cc = iselCondCode(env, e->Iex.ITE.cond);
6303 //ZZ addInstr(env, ARMInstr_VCMovS(cc ^ 1, dst, r0));
6447 //ZZ ARMCondCode cc = iselCondCode(env, sg->guard);
6449 //ZZ (cc, False/*!isLoad*/, rD, am));
6455 //ZZ ARMCondCode cc = iselCondCode(env, sg->guard);
6456 //ZZ addInstr(env, ARMInstr_LdSt16(cc,
6484 //ZZ ARMCondCode cc = iselCondCode(env, lg->guard);
6487 //ZZ (cc, True/*isLoad*/, rD, am));
6497 //ZZ ARMCondCode cc = iselCondCode(env, lg->guard);
6499 //ZZ addInstr(env, ARMInstr_Ld8S(cc, rD, am));
6503 //ZZ addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am));
6630 ARM64CondCode cc = iselCondCode(env, stmt->Ist.WrTmp.data);
6631 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
6821 ARM64CondCode cc
6838 amPC, cc, toFastEP));
6844 addInstr(env, ARM64Instr_XAssisted(r, amPC, cc, Ijk_Boring));
6860 //ZZ addInstr(env, ARMInstr_XAssisted(r, amR15T, cc,
