Lines Matching refs:instr
59 void Disassembler::VisitAddSubImmediate(Instruction* instr) {
60 bool rd_is_zr = RdIsZROrSP(instr);
61 bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) &&
62 (instr->ImmAddSub() == 0) ? true : false;
68 switch (instr->Mask(AddSubImmediateMask)) {
100 Format(instr, mnemonic, form);
104 void Disassembler::VisitAddSubShifted(Instruction* instr) {
105 bool rd_is_zr = RdIsZROrSP(instr);
106 bool rn_is_zr = RnIsZROrSP(instr);
112 switch (instr->Mask(AddSubShiftedMask)) {
147 Format(instr, mnemonic, form);
151 void Disassembler::VisitAddSubExtended(Instruction* instr) {
152 bool rd_is_zr = RdIsZROrSP(instr);
154 Extend mode = static_cast<Extend>(instr->ExtendMode());
160 switch (instr->Mask(AddSubExtendedMask)) {
185 Format(instr, mnemonic, form);
189 void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
190 bool rn_is_zr = RnIsZROrSP(instr);
195 switch (instr->Mask(AddSubWithCarryMask)) {
220 Format(instr, mnemonic, form);
224 void Disassembler::VisitLogicalImmediate(Instruction* instr) {
225 bool rd_is_zr = RdIsZROrSP(instr);
226 bool rn_is_zr = RnIsZROrSP(instr);
230 if (instr->ImmLogical() == 0) {
232 Format(instr, "unallocated", "(LogicalImmediate)");
236 switch (instr->Mask(LogicalImmediateMask)) {
242 unsigned reg_size = (instr->SixtyFourBits() != 0) ? kXRegSize
244 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
263 Format(instr, mnemonic, form);
296 void Disassembler::VisitLogicalShifted(Instruction* instr) {
297 bool rd_is_zr = RdIsZROrSP(instr);
298 bool rn_is_zr = RnIsZROrSP(instr);
302 switch (instr->Mask(LogicalShiftedMask)) {
325 if (rn_is_zr && (instr->ImmDPShift() == 0) && (instr->ShiftDP() == LSL)) {
343 Format(instr, mnemonic, form);
347 void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
351 switch (instr->Mask(ConditionalCompareRegisterMask)) {
358 Format(instr, mnemonic, form);
362 void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
366 switch (instr->Mask(ConditionalCompareImmediateMask)) {
373 Format(instr, mnemonic, form);
377 void Disassembler::VisitConditionalSelect(Instruction* instr) {
378 bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr));
379 bool rn_is_rm = (instr->Rn() == instr->Rm());
385 Condition cond = static_cast<Condition>(instr->Condition());
388 switch (instr->Mask(ConditionalSelectMask)) {
426 Format(instr, mnemonic, form);
430 void Disassembler::VisitBitfield(Instruction* instr) {
431 unsigned s = instr->ImmS();
432 unsigned r = instr->ImmR();
434 ((instr->SixtyFourBits() != 0) ? kXRegSize : kWRegSize) - 1;
443 switch (instr->Mask(BitfieldMask)) {
454 } else if ((s == 31) && (instr->SixtyFourBits() != 0)) {
504 Format(instr, mnemonic, form);
508 void Disassembler::VisitExtract(Instruction* instr) {
512 switch (instr->Mask(ExtractMask)) {
515 if (instr->Rn() == instr->Rm()) {
525 Format(instr, mnemonic, form);
529 void Disassembler::VisitPCRelAddressing(Instruction* instr) {
530 switch (instr->Mask(PCRelAddressingMask)) {
531 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break;
533 default: Format(instr, "unimplemented", "(PCRelAddressing)");
538 void Disassembler::VisitConditionalBranch(Instruction* instr) {
539 switch (instr->Mask(ConditionalBranchMask)) {
540 case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
546 void Disassembler::VisitUnconditionalBranchToRegister(Instruction* instr) {
550 switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
555 if (instr->Rn() == kLinkRegCode) {
562 Format(instr, mnemonic, form);
566 void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
570 switch (instr->Mask(UnconditionalBranchMask)) {
575 Format(instr, mnemonic, form);
579 void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
583 switch (instr->Mask(DataProcessing1SourceMask)) {
596 Format(instr, mnemonic, form);
600 void Disassembler::VisitDataProcessing2Source(Instruction* instr) {
604 switch (instr->Mask(DataProcessing2SourceMask)) {
617 Format(instr, mnemonic, form);
621 instr) {
622 bool ra_is_zr = RaIsZROrSP(instr);
630 switch (instr->Mask(DataProcessing3SourceMask)) {
695 Format(instr, mnemonic, form);
699 void Disassembler::VisitCompareBranch(Instruction* instr) {
703 switch (instr->Mask(CompareBranchMask)) {
710 Format(instr, mnemonic, form);
714 void Disassembler::VisitTestBranch(Instruction* instr) {
722 switch (instr->Mask(TestBranchMask)) {
727 Format(instr, mnemonic, form);
731 void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
738 switch (instr->Mask(MoveWideImmediateMask)) {
747 Format(instr, mnemonic, form);
770 void Disassembler::VisitLoadStorePreIndex(Instruction* instr) {
774 switch (instr->Mask(LoadStorePreIndexMask)) {
780 Format(instr, mnemonic, form);
784 void Disassembler::VisitLoadStorePostIndex(Instruction* instr) {
788 switch (instr->Mask(LoadStorePostIndexMask)) {
794 Format(instr, mnemonic, form);
798 void Disassembler::VisitLoadStoreUnsignedOffset(Instruction* instr) {
802 switch (instr->Mask(LoadStoreUnsignedOffsetMask)) {
809 Format(instr, mnemonic, form);
813 void Disassembler::VisitLoadStoreRegisterOffset(Instruction* instr) {
817 switch (instr->Mask(LoadStoreRegisterOffsetMask)) {
824 Format(instr, mnemonic, form);
828 void Disassembler::VisitLoadStoreUnscaledOffset(Instruction* instr) {
835 switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
855 Format(instr, mnemonic, form);
859 void Disassembler::VisitLoadLiteral(Instruction* instr) {
863 switch (instr->Mask(LoadLiteralMask)) {
870 Format(instr, mnemonic, form);
885 void Disassembler::VisitLoadStorePairPostIndex(Instruction* instr) {
889 switch (instr->Mask(LoadStorePairPostIndexMask)) {
895 Format(instr, mnemonic, form);
899 void Disassembler::VisitLoadStorePairPreIndex(Instruction* instr) {
903 switch (instr->Mask(LoadStorePairPreIndexMask)) {
909 Format(instr, mnemonic, form);
913 void Disassembler::VisitLoadStorePairOffset(Instruction* instr) {
917 switch (instr->Mask(LoadStorePairOffsetMask)) {
923 Format(instr, mnemonic, form);
927 void Disassembler::VisitLoadStorePairNonTemporal(Instruction* instr) {
931 switch (instr->Mask(LoadStorePairNonTemporalMask)) {
942 Format(instr, mnemonic, form);
946 void Disassembler::VisitFPCompare(Instruction* instr) {
951 switch (instr->Mask(FPCompareMask)) {
958 Format(instr, mnemonic, form);
962 void Disassembler::VisitFPConditionalCompare(Instruction* instr) {
966 switch (instr->Mask(FPConditionalCompareMask)) {
973 Format(instr, mnemonic, form);
977 void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
981 switch (instr->Mask(FPConditionalSelectMask)) {
986 Format(instr, mnemonic, form);
990 void Disassembler::VisitFPDataProcessing1Source(Instruction* instr) {
994 switch (instr->Mask(FPDataProcessing1SourceMask)) {
1014 Format(instr, mnemonic, form);
1018 void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
1022 switch (instr->Mask(FPDataProcessing2SourceMask)) {
1038 Format(instr, mnemonic, form);
1042 void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
1046 switch (instr->Mask(FPDataProcessing3SourceMask)) {
1057 Format(instr, mnemonic, form);
1061 void Disassembler::VisitFPImmediate(Instruction* instr) {
1065 switch (instr->Mask(FPImmediateMask)) {
1070 Format(instr, mnemonic, form);
1074 void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
1080 switch (instr->Mask(FPIntegerConvertMask)) {
1126 Format(instr, mnemonic, form);
1130 void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
1135 switch (instr->Mask(FPFixedPointConvertMask)) {
1154 Format(instr, mnemonic, form);
1158 void Disassembler::VisitSystem(Instruction* instr) {
1165 if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) {
1166 switch (instr->Mask(SystemSysRegMask)) {
1169 switch (instr->ImmSystemRegister()) {
1178 switch (instr->ImmSystemRegister()) {
1186 } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
1187 VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT);
1188 switch (instr->ImmHint()) {
1195 } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
1196 switch (instr->Mask(MemBarrierMask)) {
1215 Format(instr, mnemonic, form);
1219 void Disassembler::VisitException(Instruction* instr) {
1223 switch (instr->Mask(ExceptionMask)) {
1234 Format(instr, mnemonic, form);
1238 void Disassembler::VisitUnimplemented(Instruction* instr) {
1239 Format(instr, "unimplemented", "(Unimplemented)");
1243 void Disassembler::VisitUnallocated(Instruction* instr) {
1244 Format(instr, "unallocated", "(Unallocated)");
1248 void Disassembler::ProcessOutput(Instruction* /*instr*/) {
1253 void Disassembler::Format(Instruction* instr, const char* mnemonic,
1257 Substitute(instr, mnemonic);
1260 Substitute(instr, format);
1263 ProcessOutput(instr);
1267 void Disassembler::Substitute(Instruction* instr, const char* string) {
1271 string += SubstituteField(instr, string);
1280 int Disassembler::SubstituteField(Instruction* instr, const char* format) {
1287 case 'D': return SubstituteRegisterField(instr, format);
1288 case 'I': return SubstituteImmediateField(instr, format);
1289 case 'L': return SubstituteLiteralField(instr, format);
1290 case 'H': return SubstituteShiftField(instr, format);
1291 case 'P': return SubstitutePrefetchField(instr, format);
1292 case 'C': return SubstituteConditionField(instr, format);
1293 case 'E': return SubstituteExtendField(instr, format);
1294 case 'A': return SubstitutePCRelAddressField(instr, format);
1295 case 'B': return SubstituteBranchTargetField(instr, format);
1296 case 'O': return SubstituteLSRegOffsetField(instr, format);
1297 case 'M': return SubstituteBarrierField(instr, format);
1306 int Disassembler::SubstituteRegisterField(Instruction* instr,
1311 case 'd': reg_num = instr->Rd(); break;
1312 case 'n': reg_num = instr->Rn(); break;
1313 case 'm': reg_num = instr->Rm(); break;
1314 case 'a': reg_num = instr->Ra(); break;
1317 reg_num = instr->Rt2();
1320 reg_num = instr->Rt();
1335 reg_type = instr->SixtyFourBits() ? 'x' : 'w';
1338 reg_type = ((instr->FPType() & 1) == 0) ? 's' : 'd';
1359 int Disassembler::SubstituteImmediateField(Instruction* instr,
1366 uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
1370 AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
1371 if (instr->ShiftMoveWide() > 0) {
1372 AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
1381 instr->ImmLLiteral() << kLiteralEntrySizeLog2);
1385 if (instr->ImmLS() != 0) {
1386 AppendToOutput(", #%" PRId64, instr->ImmLS());
1391 if (instr->ImmLSPair() != 0) {
1394 AppendToOutput(", #%" PRId64, instr->ImmLSPair() * scale);
1399 if (instr->ImmLSUnsigned() != 0) {
1401 instr->ImmLSUnsigned() << instr->SizeLS());
1408 int64_t offset = instr->ImmCondBranch() << 2;
1414 VIXL_ASSERT(instr->ShiftAddSub() <= 1);
1415 int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
1421 AppendToOutput("#%d", 64 - instr->FPScale());
1424 AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
1425 format[3] == 'S' ? instr->ImmFP32() : instr->ImmFP64());
1430 AppendToOutput("#0x%" PRIx64, instr->ImmLogical());
1434 int nzcv = (instr->Nzcv() << Flags_offset);
1442 AppendToOutput("#%d", instr->ImmCondCmp());
1446 return SubstituteBitfieldImmediateField(instr, format);
1449 AppendToOutput("#%d", instr->ImmS());
1453 AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
1454 instr->ImmTestBranchBit40());
1458 AppendToOutput("#0x%x", instr->ImmException());
1469 int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
1472 unsigned r = instr->ImmR();
1473 unsigned s = instr->ImmS();
1492 unsigned reg_size = (instr->SixtyFourBits() != 0) ? kXRegSize : kWRegSize;
1504 int Disassembler::SubstituteLiteralField(Instruction* instr,
1509 switch (instr->Mask(LoadLiteralMask)) {
1513 case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
1521 int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
1523 VIXL_ASSERT(instr->ShiftDP() <= 0x3);
1527 VIXL_ASSERT(instr->ShiftDP() != ROR);
1530 if (instr->ImmDPShift() != 0) {
1532 AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()],
1533 instr->ImmDPShift());
1544 int Disassembler::SubstituteConditionField(Instruction* instr,
1553 case 'B': cond = instr->ConditionBranch(); break;
1555 cond = InvertCondition(static_cast<Condition>(instr->Condition()));
1558 default: cond = instr->Condition();
1565 int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
1570 int offset = instr->ImmPCRel();
1580 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
1581 AppendToOutput("#%c0x%x (addr %p)", sign, offset, instr + offset);
1586 int Disassembler::SubstituteBranchTargetField(Instruction* instr,
1593 case 'n': offset = instr->ImmUncondBranch(); break;
1595 case 'o': offset = instr->ImmCondBranch(); break;
1597 case 'm': offset = instr->ImmCmpBranch(); break;
1599 case 'e': offset = instr->ImmTestBranch(); break;
1608 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
1609 AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, offset, instr + offset);
1614 int Disassembler::SubstituteExtendField(Instruction* instr,
1617 VIXL_ASSERT(instr->ExtendMode() <= 7);
1625 if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) &&
1626 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
1627 (instr->ExtendMode() == UXTX))) {
1628 if (instr->ImmExtendShift() > 0) {
1629 AppendToOutput(", lsl #%d", instr->ImmExtendShift());
1632 AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
1633 if (instr->ImmExtendShift() > 0) {
1634 AppendToOutput(" #%d", instr->ImmExtendShift());
1641 int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
1648 unsigned shift = instr->ImmShiftLS();
1649 Extend ext = static_cast<Extend>(instr->ExtendMode());
1652 unsigned rm = instr->Rm();
1663 AppendToOutput(" #%d", instr->SizeLS());
1670 int Disassembler::SubstitutePrefetchField(Instruction* instr,
1675 int prefetch_mode = instr->PrefetchMode();
1685 int Disassembler::SubstituteBarrierField(Instruction* instr,
1696 int domain = instr->ImmBarrierDomain();
1697 int type = instr->ImmBarrierType();
1717 void PrintDisassembler::ProcessOutput(Instruction* instr) {
1719 reinterpret_cast<uint64_t>(instr),
1720 instr->InstructionBits(),
