| /external/vixl/src/a64/ |
| assembler-a64.h | 81 RegList Bit() const {
312 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
420 return (type_ == other.type()) && ((other.Bit() & list_) != 0);
714 // Test bit and branch to label if zero.
717 // Test bit and branch to PC offset if zero.
720 // Test bit and branch to label if not zero.
723 // Test bit and branch to PC offset if not zero
[all...] |
| instructions-a64.h | 164 inline int Bit(int pos) const {
|
| /art/compiler/dex/quick/ |
| resource_mask.h | 42 * Def/Use encoding in 128-bit use_mask/def_mask. Low positions used for target-specific
75 static constexpr ResourceMask Bit(size_t bit) {
76 return ResourceMask(bit >= 64u ? 0u : UINT64_C(1) << bit,
77 bit >= 64u ? UINT64_C(1) << (bit - 64u) : 0u);
83 DCHECK_CONSTEXPR((start_bit & 1u) == 0u, << start_bit << " isn't even", Bit(0))
116 void SetBit(size_t bit) {
117 DCHECK_LE(bit, kHighestCommonResource)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 161 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
204 unsigned Bit = 0;
210 REX |= 1 << Bit;
211 Bit++;
226 unsigned Bit = 0;
231 REX |= 1 << Bit;
232 Bit++;
392 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
401 // mechanism as 32-bit mode.
429 // In 64-bit static small code model, we could potentially emit absolute
[all...] |
| /external/llvm/lib/TableGen/ |
| TGLexer.h | 46 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
|
| TGParser.cpp | 113 return Error(Loc, "Initializer is not compatible with bit range");
124 unsigned Bit = BitList[i];
125 if (NewBits[Bit])
126 return Error(Loc, "Cannot set bit #" + utostr(Bit) + " of value '" +
128 NewBits[Bit] = BInit->getBit(i);
562 /// ParseRangePiece - Parse a bit/value range.
649 /// ParseOptionalBitList - Parse either a bit list in {}'s or nothing.
664 TokError("expected '}' at end of bit list");
676 /// Type ::= BIT // bit typ
[all...] |
| Record.cpp | 104 if (BI->getNumBits() != 1) return nullptr; // Only accept if just one bit!
110 if (Val != 0 && Val != 1) return nullptr; // Only accept 0 or 1 for a bit!
118 return VI; // Accept variable if it is already of bit type!
154 if (Size != 1) return nullptr; // Can only convert single bit.
219 if (BitInit *Bit = dyn_cast<BitInit>(BI->getBit(i))) {
220 Result |= Bit->getValue() << i;
495 if (Init *Bit = getBit(e-i-1))
496 Result += Bit->getAsString();
503 // Fix bit initializer to preserve the behavior that bit reference from a unse
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| assembler-arm64-inl.h | 51 inline RegList CPURegister::Bit() const {
360 // Extend modes SXTX and UXTX require a 64-bit register.
473 // SXTX extend mode requires a 64-bit offset register.
1035 // Subtract five from the shift offset, as we need bit 5 from bit_pos.
[all...] |
| instructions-arm64.h | 21 // The following macros initialize a float/double variable with a bit pattern
23 // symbol is defined as uint32_t/uint64_t initialized with the desired bit
107 int Bit(int pos) const {
427 // - arg_pattern: A set of PrintfArgPattern values, packed into two-bit fields.
441 // The argument pattern is a set of two-bit-fields, each with one of the
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
179 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
185 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
189 "Compressed 8-bit displacement is only valid for EVEX inst.");
247 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
261 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
402 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
428 // 16-bit addressing forms of the ModR/M byte have a different encoding for
432 // For 32-bit addressing, the row and column values in Table 2-2 are
435 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A
[all...] |
| /external/llvm/include/llvm/Support/ |
| CommandLine.h | [all...] |
| /art/compiler/utils/arm/ |
| constants_arm.h | 145 BIC = 14, // Bit Clear
254 // Read one particular bit out of the instruction bits.
255 int Bit(int nr) const {
259 // Read a bit field out of the instruction bits.
289 int RegShiftField() const { return Bit(4); }
301 int BField() const { return Bit(22); }
302 int WField() const { return Bit(21); }
303 int LField() const { return Bit(20); }
311 int SignField() const { return Bit(6); }
312 int HField() const { return Bit(5);
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 140 /// BitRecTy - 'bit' - Represent a single bit
169 std::string getAsString() const override { return "bit"; }
430 /// We could pack these a bit tighter by not having the IK_FirstXXXInit
498 /// the bit subscript operator on this initializer, return null.
542 /// bit.
543 virtual Init *getBit(unsigned Bit) const = 0;
545 /// getBitVar - This method is used to retrieve the initializer for bit
549 /// getBitNum - This method is used to retrieve the bit number of a bit
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 595 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
658 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 120 // Instr is merely used by the Assembler to distinguish 32bit integers
121 // representing instructions from usual 32 bit values.
122 // Instruction objects are pointers to 32bit values, and provide methods to
144 BIC = 14 << 21, // Bit Clear.
149 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
196 // Instruction bit masks.
261 // Bit encoding P U W.
273 // Bit encoding P U W .
331 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
332 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature
[all...] |
| /external/clang/lib/CodeGen/ |
| MicrosoftCXXABI.cpp | 123 // The deleting destructors accept an i32 bitfield as a second parameter. Bit
124 // 1 indicates if the memory should be deleted. Bit 2 indicates if the this
126 // bit 2 is zero, and therefore does not contain a loop.
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 31 // (((X ^ XORValue) + AddValue) >> Bit)
33 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
34 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
38 unsigned Bit;
63 // Classify VT as either 32 or 64 bit.
185 // Type legalization will convert 8- and 16-bit atomic operations into
202 // Handle unsigned 32-bit types as signed 64-bit types.
208 // We have native support for a 64-bit CTLZ, via FLOGR
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 474 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
[all...] |
