1 //===-- ARM_DWARF_Registers.c -----------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARM_DWARF_Registers.h" 11 #include <string.h> 12 13 #include <string.h> 14 15 using namespace lldb; 16 using namespace lldb_private; 17 18 const char * 19 GetARMDWARFRegisterName (unsigned reg_num) 20 { 21 switch (reg_num) 22 { 23 case dwarf_r0: return "r0"; 24 case dwarf_r1: return "r1"; 25 case dwarf_r2: return "r2"; 26 case dwarf_r3: return "r3"; 27 case dwarf_r4: return "r4"; 28 case dwarf_r5: return "r5"; 29 case dwarf_r6: return "r6"; 30 case dwarf_r7: return "r7"; 31 case dwarf_r8: return "r8"; 32 case dwarf_r9: return "r9"; 33 case dwarf_r10: return "r10"; 34 case dwarf_r11: return "r11"; 35 case dwarf_r12: return "r12"; 36 case dwarf_sp: return "sp"; 37 case dwarf_lr: return "lr"; 38 case dwarf_pc: return "pc"; 39 case dwarf_cpsr:return "cpsr"; 40 41 case dwarf_s0: return "s0"; 42 case dwarf_s1: return "s1"; 43 case dwarf_s2: return "s2"; 44 case dwarf_s3: return "s3"; 45 case dwarf_s4: return "s4"; 46 case dwarf_s5: return "s5"; 47 case dwarf_s6: return "s6"; 48 case dwarf_s7: return "s7"; 49 case dwarf_s8: return "s8"; 50 case dwarf_s9: return "s9"; 51 case dwarf_s10: return "s10"; 52 case dwarf_s11: return "s11"; 53 case dwarf_s12: return "s12"; 54 case dwarf_s13: return "s13"; 55 case dwarf_s14: return "s14"; 56 case dwarf_s15: return "s15"; 57 case dwarf_s16: return "s16"; 58 case dwarf_s17: return "s17"; 59 case dwarf_s18: return "s18"; 60 case dwarf_s19: return "s19"; 61 case dwarf_s20: return "s20"; 62 case dwarf_s21: return "s21"; 63 case dwarf_s22: return "s22"; 64 case dwarf_s23: return "s23"; 65 case dwarf_s24: return "s24"; 66 case dwarf_s25: return "s25"; 67 case dwarf_s26: return "s26"; 68 case dwarf_s27: return "s27"; 69 case dwarf_s28: return "s28"; 70 case dwarf_s29: return "s29"; 71 case dwarf_s30: return "s30"; 72 case dwarf_s31: return "s31"; 73 74 // FPA Registers 0-7 75 case dwarf_f0: return "f0"; 76 case dwarf_f1: return "f1"; 77 case dwarf_f2: return "f2"; 78 case dwarf_f3: return "f3"; 79 case dwarf_f4: return "f4"; 80 case dwarf_f5: return "f5"; 81 case dwarf_f6: return "f6"; 82 case dwarf_f7: return "f7"; 83 84 // Intel wireless MMX general purpose registers 0 - 7 85 // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7) 86 case dwarf_wCGR0: return "wCGR0/ACC0"; 87 case dwarf_wCGR1: return "wCGR1/ACC1"; 88 case dwarf_wCGR2: return "wCGR2/ACC2"; 89 case dwarf_wCGR3: return "wCGR3/ACC3"; 90 case dwarf_wCGR4: return "wCGR4/ACC4"; 91 case dwarf_wCGR5: return "wCGR5/ACC5"; 92 case dwarf_wCGR6: return "wCGR6/ACC6"; 93 case dwarf_wCGR7: return "wCGR7/ACC7"; 94 95 // Intel wireless MMX data registers 0 - 15 96 case dwarf_wR0: return "wR0"; 97 case dwarf_wR1: return "wR1"; 98 case dwarf_wR2: return "wR2"; 99 case dwarf_wR3: return "wR3"; 100 case dwarf_wR4: return "wR4"; 101 case dwarf_wR5: return "wR5"; 102 case dwarf_wR6: return "wR6"; 103 case dwarf_wR7: return "wR7"; 104 case dwarf_wR8: return "wR8"; 105 case dwarf_wR9: return "wR9"; 106 case dwarf_wR10: return "wR10"; 107 case dwarf_wR11: return "wR11"; 108 case dwarf_wR12: return "wR12"; 109 case dwarf_wR13: return "wR13"; 110 case dwarf_wR14: return "wR14"; 111 case dwarf_wR15: return "wR15"; 112 113 case dwarf_spsr: return "spsr"; 114 case dwarf_spsr_fiq: return "spsr_fiq"; 115 case dwarf_spsr_irq: return "spsr_irq"; 116 case dwarf_spsr_abt: return "spsr_abt"; 117 case dwarf_spsr_und: return "spsr_und"; 118 case dwarf_spsr_svc: return "spsr_svc"; 119 120 case dwarf_r8_usr: return "r8_usr"; 121 case dwarf_r9_usr: return "r9_usr"; 122 case dwarf_r10_usr: return "r10_usr"; 123 case dwarf_r11_usr: return "r11_usr"; 124 case dwarf_r12_usr: return "r12_usr"; 125 case dwarf_r13_usr: return "r13_usr"; 126 case dwarf_r14_usr: return "r14_usr"; 127 case dwarf_r8_fiq: return "r8_fiq"; 128 case dwarf_r9_fiq: return "r9_fiq"; 129 case dwarf_r10_fiq: return "r10_fiq"; 130 case dwarf_r11_fiq: return "r11_fiq"; 131 case dwarf_r12_fiq: return "r12_fiq"; 132 case dwarf_r13_fiq: return "r13_fiq"; 133 case dwarf_r14_fiq: return "r14_fiq"; 134 case dwarf_r13_irq: return "r13_irq"; 135 case dwarf_r14_irq: return "r14_irq"; 136 case dwarf_r13_abt: return "r13_abt"; 137 case dwarf_r14_abt: return "r14_abt"; 138 case dwarf_r13_und: return "r13_und"; 139 case dwarf_r14_und: return "r14_und"; 140 case dwarf_r13_svc: return "r13_svc"; 141 case dwarf_r14_svc: return "r14_svc"; 142 143 // Intel wireless MMX control register in co-processor 0 - 7 144 case dwarf_wC0: return "wC0"; 145 case dwarf_wC1: return "wC1"; 146 case dwarf_wC2: return "wC2"; 147 case dwarf_wC3: return "wC3"; 148 case dwarf_wC4: return "wC4"; 149 case dwarf_wC5: return "wC5"; 150 case dwarf_wC6: return "wC6"; 151 case dwarf_wC7: return "wC7"; 152 153 // VFP-v3/Neon 154 case dwarf_d0: return "d0"; 155 case dwarf_d1: return "d1"; 156 case dwarf_d2: return "d2"; 157 case dwarf_d3: return "d3"; 158 case dwarf_d4: return "d4"; 159 case dwarf_d5: return "d5"; 160 case dwarf_d6: return "d6"; 161 case dwarf_d7: return "d7"; 162 case dwarf_d8: return "d8"; 163 case dwarf_d9: return "d9"; 164 case dwarf_d10: return "d10"; 165 case dwarf_d11: return "d11"; 166 case dwarf_d12: return "d12"; 167 case dwarf_d13: return "d13"; 168 case dwarf_d14: return "d14"; 169 case dwarf_d15: return "d15"; 170 case dwarf_d16: return "d16"; 171 case dwarf_d17: return "d17"; 172 case dwarf_d18: return "d18"; 173 case dwarf_d19: return "d19"; 174 case dwarf_d20: return "d20"; 175 case dwarf_d21: return "d21"; 176 case dwarf_d22: return "d22"; 177 case dwarf_d23: return "d23"; 178 case dwarf_d24: return "d24"; 179 case dwarf_d25: return "d25"; 180 case dwarf_d26: return "d26"; 181 case dwarf_d27: return "d27"; 182 case dwarf_d28: return "d28"; 183 case dwarf_d29: return "d29"; 184 case dwarf_d30: return "d30"; 185 case dwarf_d31: return "d31"; 186 187 // NEON 128-bit vector registers (overlays the d registers) 188 case dwarf_q0: return "q0"; 189 case dwarf_q1: return "q1"; 190 case dwarf_q2: return "q2"; 191 case dwarf_q3: return "q3"; 192 case dwarf_q4: return "q4"; 193 case dwarf_q5: return "q5"; 194 case dwarf_q6: return "q6"; 195 case dwarf_q7: return "q7"; 196 case dwarf_q8: return "q8"; 197 case dwarf_q9: return "q9"; 198 case dwarf_q10: return "q10"; 199 case dwarf_q11: return "q11"; 200 case dwarf_q12: return "q12"; 201 case dwarf_q13: return "q13"; 202 case dwarf_q14: return "q14"; 203 case dwarf_q15: return "q15"; 204 } 205 return 0; 206 } 207 208 bool 209 GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) 210 { 211 ::memset (®_info, 0, sizeof(RegisterInfo)); 212 ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); 213 214 if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) 215 { 216 reg_info.byte_size = 16; 217 reg_info.format = eFormatVectorOfUInt8; 218 reg_info.encoding = eEncodingVector; 219 } 220 221 if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) 222 { 223 reg_info.byte_size = 8; 224 reg_info.format = eFormatFloat; 225 reg_info.encoding = eEncodingIEEE754; 226 } 227 else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) 228 { 229 reg_info.byte_size = 4; 230 reg_info.format = eFormatFloat; 231 reg_info.encoding = eEncodingIEEE754; 232 } 233 else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) 234 { 235 reg_info.byte_size = 12; 236 reg_info.format = eFormatFloat; 237 reg_info.encoding = eEncodingIEEE754; 238 } 239 else 240 { 241 reg_info.byte_size = 4; 242 reg_info.format = eFormatHex; 243 reg_info.encoding = eEncodingUint; 244 } 245 246 reg_info.kinds[eRegisterKindDWARF] = reg_num; 247 248 switch (reg_num) 249 { 250 case dwarf_r0: reg_info.name = "r0"; break; 251 case dwarf_r1: reg_info.name = "r1"; break; 252 case dwarf_r2: reg_info.name = "r2"; break; 253 case dwarf_r3: reg_info.name = "r3"; break; 254 case dwarf_r4: reg_info.name = "r4"; break; 255 case dwarf_r5: reg_info.name = "r5"; break; 256 case dwarf_r6: reg_info.name = "r6"; break; 257 case dwarf_r7: reg_info.name = "r7"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; 258 case dwarf_r8: reg_info.name = "r8"; break; 259 case dwarf_r9: reg_info.name = "r9"; break; 260 case dwarf_r10: reg_info.name = "r10"; break; 261 case dwarf_r11: reg_info.name = "r11"; break; 262 case dwarf_r12: reg_info.name = "r12"; break; 263 case dwarf_sp: reg_info.name = "sp"; reg_info.alt_name = "r13"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; 264 case dwarf_lr: reg_info.name = "lr"; reg_info.alt_name = "r14"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; 265 case dwarf_pc: reg_info.name = "pc"; reg_info.alt_name = "r15"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; 266 case dwarf_cpsr:reg_info.name = "cpsr"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; 267 268 case dwarf_s0: reg_info.name = "s0"; break; 269 case dwarf_s1: reg_info.name = "s1"; break; 270 case dwarf_s2: reg_info.name = "s2"; break; 271 case dwarf_s3: reg_info.name = "s3"; break; 272 case dwarf_s4: reg_info.name = "s4"; break; 273 case dwarf_s5: reg_info.name = "s5"; break; 274 case dwarf_s6: reg_info.name = "s6"; break; 275 case dwarf_s7: reg_info.name = "s7"; break; 276 case dwarf_s8: reg_info.name = "s8"; break; 277 case dwarf_s9: reg_info.name = "s9"; break; 278 case dwarf_s10: reg_info.name = "s10"; break; 279 case dwarf_s11: reg_info.name = "s11"; break; 280 case dwarf_s12: reg_info.name = "s12"; break; 281 case dwarf_s13: reg_info.name = "s13"; break; 282 case dwarf_s14: reg_info.name = "s14"; break; 283 case dwarf_s15: reg_info.name = "s15"; break; 284 case dwarf_s16: reg_info.name = "s16"; break; 285 case dwarf_s17: reg_info.name = "s17"; break; 286 case dwarf_s18: reg_info.name = "s18"; break; 287 case dwarf_s19: reg_info.name = "s19"; break; 288 case dwarf_s20: reg_info.name = "s20"; break; 289 case dwarf_s21: reg_info.name = "s21"; break; 290 case dwarf_s22: reg_info.name = "s22"; break; 291 case dwarf_s23: reg_info.name = "s23"; break; 292 case dwarf_s24: reg_info.name = "s24"; break; 293 case dwarf_s25: reg_info.name = "s25"; break; 294 case dwarf_s26: reg_info.name = "s26"; break; 295 case dwarf_s27: reg_info.name = "s27"; break; 296 case dwarf_s28: reg_info.name = "s28"; break; 297 case dwarf_s29: reg_info.name = "s29"; break; 298 case dwarf_s30: reg_info.name = "s30"; break; 299 case dwarf_s31: reg_info.name = "s31"; break; 300 301 // FPA Registers 0-7 302 case dwarf_f0: reg_info.name = "f0"; break; 303 case dwarf_f1: reg_info.name = "f1"; break; 304 case dwarf_f2: reg_info.name = "f2"; break; 305 case dwarf_f3: reg_info.name = "f3"; break; 306 case dwarf_f4: reg_info.name = "f4"; break; 307 case dwarf_f5: reg_info.name = "f5"; break; 308 case dwarf_f6: reg_info.name = "f6"; break; 309 case dwarf_f7: reg_info.name = "f7"; break; 310 311 // Intel wireless MMX general purpose registers 0 - 7 312 // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7) 313 case dwarf_wCGR0: reg_info.name = "wCGR0/ACC0"; break; 314 case dwarf_wCGR1: reg_info.name = "wCGR1/ACC1"; break; 315 case dwarf_wCGR2: reg_info.name = "wCGR2/ACC2"; break; 316 case dwarf_wCGR3: reg_info.name = "wCGR3/ACC3"; break; 317 case dwarf_wCGR4: reg_info.name = "wCGR4/ACC4"; break; 318 case dwarf_wCGR5: reg_info.name = "wCGR5/ACC5"; break; 319 case dwarf_wCGR6: reg_info.name = "wCGR6/ACC6"; break; 320 case dwarf_wCGR7: reg_info.name = "wCGR7/ACC7"; break; 321 322 // Intel wireless MMX data registers 0 - 15 323 case dwarf_wR0: reg_info.name = "wR0"; break; 324 case dwarf_wR1: reg_info.name = "wR1"; break; 325 case dwarf_wR2: reg_info.name = "wR2"; break; 326 case dwarf_wR3: reg_info.name = "wR3"; break; 327 case dwarf_wR4: reg_info.name = "wR4"; break; 328 case dwarf_wR5: reg_info.name = "wR5"; break; 329 case dwarf_wR6: reg_info.name = "wR6"; break; 330 case dwarf_wR7: reg_info.name = "wR7"; break; 331 case dwarf_wR8: reg_info.name = "wR8"; break; 332 case dwarf_wR9: reg_info.name = "wR9"; break; 333 case dwarf_wR10: reg_info.name = "wR10"; break; 334 case dwarf_wR11: reg_info.name = "wR11"; break; 335 case dwarf_wR12: reg_info.name = "wR12"; break; 336 case dwarf_wR13: reg_info.name = "wR13"; break; 337 case dwarf_wR14: reg_info.name = "wR14"; break; 338 case dwarf_wR15: reg_info.name = "wR15"; break; 339 340 case dwarf_spsr: reg_info.name = "spsr"; break; 341 case dwarf_spsr_fiq: reg_info.name = "spsr_fiq"; break; 342 case dwarf_spsr_irq: reg_info.name = "spsr_irq"; break; 343 case dwarf_spsr_abt: reg_info.name = "spsr_abt"; break; 344 case dwarf_spsr_und: reg_info.name = "spsr_und"; break; 345 case dwarf_spsr_svc: reg_info.name = "spsr_svc"; break; 346 347 case dwarf_r8_usr: reg_info.name = "r8_usr"; break; 348 case dwarf_r9_usr: reg_info.name = "r9_usr"; break; 349 case dwarf_r10_usr: reg_info.name = "r10_usr"; break; 350 case dwarf_r11_usr: reg_info.name = "r11_usr"; break; 351 case dwarf_r12_usr: reg_info.name = "r12_usr"; break; 352 case dwarf_r13_usr: reg_info.name = "r13_usr"; break; 353 case dwarf_r14_usr: reg_info.name = "r14_usr"; break; 354 case dwarf_r8_fiq: reg_info.name = "r8_fiq"; break; 355 case dwarf_r9_fiq: reg_info.name = "r9_fiq"; break; 356 case dwarf_r10_fiq: reg_info.name = "r10_fiq"; break; 357 case dwarf_r11_fiq: reg_info.name = "r11_fiq"; break; 358 case dwarf_r12_fiq: reg_info.name = "r12_fiq"; break; 359 case dwarf_r13_fiq: reg_info.name = "r13_fiq"; break; 360 case dwarf_r14_fiq: reg_info.name = "r14_fiq"; break; 361 case dwarf_r13_irq: reg_info.name = "r13_irq"; break; 362 case dwarf_r14_irq: reg_info.name = "r14_irq"; break; 363 case dwarf_r13_abt: reg_info.name = "r13_abt"; break; 364 case dwarf_r14_abt: reg_info.name = "r14_abt"; break; 365 case dwarf_r13_und: reg_info.name = "r13_und"; break; 366 case dwarf_r14_und: reg_info.name = "r14_und"; break; 367 case dwarf_r13_svc: reg_info.name = "r13_svc"; break; 368 case dwarf_r14_svc: reg_info.name = "r14_svc"; break; 369 370 // Intel wireless MMX control register in co-processor 0 - 7 371 case dwarf_wC0: reg_info.name = "wC0"; break; 372 case dwarf_wC1: reg_info.name = "wC1"; break; 373 case dwarf_wC2: reg_info.name = "wC2"; break; 374 case dwarf_wC3: reg_info.name = "wC3"; break; 375 case dwarf_wC4: reg_info.name = "wC4"; break; 376 case dwarf_wC5: reg_info.name = "wC5"; break; 377 case dwarf_wC6: reg_info.name = "wC6"; break; 378 case dwarf_wC7: reg_info.name = "wC7"; break; 379 380 // VFP-v3/Neon 381 case dwarf_d0: reg_info.name = "d0"; break; 382 case dwarf_d1: reg_info.name = "d1"; break; 383 case dwarf_d2: reg_info.name = "d2"; break; 384 case dwarf_d3: reg_info.name = "d3"; break; 385 case dwarf_d4: reg_info.name = "d4"; break; 386 case dwarf_d5: reg_info.name = "d5"; break; 387 case dwarf_d6: reg_info.name = "d6"; break; 388 case dwarf_d7: reg_info.name = "d7"; break; 389 case dwarf_d8: reg_info.name = "d8"; break; 390 case dwarf_d9: reg_info.name = "d9"; break; 391 case dwarf_d10: reg_info.name = "d10"; break; 392 case dwarf_d11: reg_info.name = "d11"; break; 393 case dwarf_d12: reg_info.name = "d12"; break; 394 case dwarf_d13: reg_info.name = "d13"; break; 395 case dwarf_d14: reg_info.name = "d14"; break; 396 case dwarf_d15: reg_info.name = "d15"; break; 397 case dwarf_d16: reg_info.name = "d16"; break; 398 case dwarf_d17: reg_info.name = "d17"; break; 399 case dwarf_d18: reg_info.name = "d18"; break; 400 case dwarf_d19: reg_info.name = "d19"; break; 401 case dwarf_d20: reg_info.name = "d20"; break; 402 case dwarf_d21: reg_info.name = "d21"; break; 403 case dwarf_d22: reg_info.name = "d22"; break; 404 case dwarf_d23: reg_info.name = "d23"; break; 405 case dwarf_d24: reg_info.name = "d24"; break; 406 case dwarf_d25: reg_info.name = "d25"; break; 407 case dwarf_d26: reg_info.name = "d26"; break; 408 case dwarf_d27: reg_info.name = "d27"; break; 409 case dwarf_d28: reg_info.name = "d28"; break; 410 case dwarf_d29: reg_info.name = "d29"; break; 411 case dwarf_d30: reg_info.name = "d30"; break; 412 case dwarf_d31: reg_info.name = "d31"; break; 413 414 // NEON 128-bit vector registers (overlays the d registers) 415 case dwarf_q0: reg_info.name = "q0"; break; 416 case dwarf_q1: reg_info.name = "q1"; break; 417 case dwarf_q2: reg_info.name = "q2"; break; 418 case dwarf_q3: reg_info.name = "q3"; break; 419 case dwarf_q4: reg_info.name = "q4"; break; 420 case dwarf_q5: reg_info.name = "q5"; break; 421 case dwarf_q6: reg_info.name = "q6"; break; 422 case dwarf_q7: reg_info.name = "q7"; break; 423 case dwarf_q8: reg_info.name = "q8"; break; 424 case dwarf_q9: reg_info.name = "q9"; break; 425 case dwarf_q10: reg_info.name = "q10"; break; 426 case dwarf_q11: reg_info.name = "q11"; break; 427 case dwarf_q12: reg_info.name = "q12"; break; 428 case dwarf_q13: reg_info.name = "q13"; break; 429 case dwarf_q14: reg_info.name = "q14"; break; 430 case dwarf_q15: reg_info.name = "q15"; break; 431 432 default: return false; 433 } 434 return true; 435 } 436
