1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of GDB, GAS, and the GNU binutils. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "disas/bfd.h" 23 24 /* mips.h. Mips opcode list for GDB, the GNU debugger. 25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 26 Free Software Foundation, Inc. 27 Contributed by Ralph Campbell and OSF 28 Commented and modified by Ian Lance Taylor, Cygnus Support 29 30 This file is part of GDB, GAS, and the GNU binutils. 31 32 GDB, GAS, and the GNU binutils are free software; you can redistribute 33 them and/or modify them under the terms of the GNU General Public 34 License as published by the Free Software Foundation; either version 35 1, or (at your option) any later version. 36 37 GDB, GAS, and the GNU binutils are distributed in the hope that they 38 will be useful, but WITHOUT ANY WARRANTY; without even the implied 39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 40 the GNU General Public License for more details. 41 42 You should have received a copy of the GNU General Public License 43 along with this file; see the file COPYING. If not, 44 see <http://www.gnu.org/licenses/>. */ 45 46 /* These are bit masks and shift counts to use to access the various 47 fields of an instruction. To retrieve the X field of an 48 instruction, use the expression 49 (i >> OP_SH_X) & OP_MASK_X 50 To set the same field (to j), use 51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 52 53 Make sure you use fields that are appropriate for the instruction, 54 of course. 55 56 The 'i' format uses OP, RS, RT and IMMEDIATE. 57 58 The 'j' format uses OP and TARGET. 59 60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 61 62 The 'b' format uses OP, RS, RT and DELTA. 63 64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 65 66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 67 68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 69 breakpoint instruction are not defined; Kane says the breakpoint 70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 71 only use ten bits). An optional two-operand form of break/sdbbp 72 allows the lower ten bits to be set too, and MIPS32 and later 73 architectures allow 20 bits to be set with a signal operand 74 (using CODE20). 75 76 The syscall instruction uses CODE20. 77 78 The general coprocessor instructions use COPZ. */ 79 80 #define OP_MASK_OP 0x3f 81 #define OP_SH_OP 26 82 #define OP_MASK_RS 0x1f 83 #define OP_SH_RS 21 84 #define OP_MASK_FR 0x1f 85 #define OP_SH_FR 21 86 #define OP_MASK_FMT 0x1f 87 #define OP_SH_FMT 21 88 #define OP_MASK_BCC 0x7 89 #define OP_SH_BCC 18 90 #define OP_MASK_CODE 0x3ff 91 #define OP_SH_CODE 16 92 #define OP_MASK_CODE2 0x3ff 93 #define OP_SH_CODE2 6 94 #define OP_MASK_RT 0x1f 95 #define OP_SH_RT 16 96 #define OP_MASK_FT 0x1f 97 #define OP_SH_FT 16 98 #define OP_MASK_CACHE 0x1f 99 #define OP_SH_CACHE 16 100 #define OP_MASK_RD 0x1f 101 #define OP_SH_RD 11 102 #define OP_MASK_FS 0x1f 103 #define OP_SH_FS 11 104 #define OP_MASK_PREFX 0x1f 105 #define OP_SH_PREFX 11 106 #define OP_MASK_CCC 0x7 107 #define OP_SH_CCC 8 108 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 109 #define OP_SH_CODE20 6 110 #define OP_MASK_SHAMT 0x1f 111 #define OP_SH_SHAMT 6 112 #define OP_MASK_FD 0x1f 113 #define OP_SH_FD 6 114 #define OP_MASK_TARGET 0x3ffffff 115 #define OP_SH_TARGET 0 116 #define OP_MASK_COPZ 0x1ffffff 117 #define OP_SH_COPZ 0 118 #define OP_MASK_IMMEDIATE 0xffff 119 #define OP_SH_IMMEDIATE 0 120 #define OP_MASK_DELTA 0xffff 121 #define OP_SH_DELTA 0 122 #define OP_MASK_FUNCT 0x3f 123 #define OP_SH_FUNCT 0 124 #define OP_MASK_SPEC 0x3f 125 #define OP_SH_SPEC 0 126 #define OP_SH_LOCC 8 /* FP condition code. */ 127 #define OP_SH_HICC 18 /* FP condition code. */ 128 #define OP_MASK_CC 0x7 129 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 130 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 131 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 132 #define OP_MASK_COP1SPEC 0xf 133 #define OP_MASK_COP1SCLR 0x4 134 #define OP_MASK_COP1CMP 0x3 135 #define OP_SH_COP1CMP 4 136 #define OP_SH_FORMAT 21 /* FP short format field. */ 137 #define OP_MASK_FORMAT 0x7 138 #define OP_SH_TRUE 16 139 #define OP_MASK_TRUE 0x1 140 #define OP_SH_GE 17 141 #define OP_MASK_GE 0x01 142 #define OP_SH_UNSIGNED 16 143 #define OP_MASK_UNSIGNED 0x1 144 #define OP_SH_HINT 16 145 #define OP_MASK_HINT 0x1f 146 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 147 #define OP_MASK_MMI 0x3f 148 #define OP_SH_MMISUB 6 149 #define OP_MASK_MMISUB 0x1f 150 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 151 #define OP_SH_PERFREG 1 152 #define OP_SH_SEL 0 /* Coprocessor select field. */ 153 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 154 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 155 #define OP_MASK_CODE19 0x7ffff 156 #define OP_SH_ALN 21 157 #define OP_MASK_ALN 0x7 158 #define OP_SH_VSEL 21 159 #define OP_MASK_VSEL 0x1f 160 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 161 but 0x8-0xf don't select bytes. */ 162 #define OP_SH_VECBYTE 22 163 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 164 #define OP_SH_VECALIGN 21 165 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 166 #define OP_SH_INSMSB 11 167 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 168 #define OP_SH_EXTMSBD 11 169 170 #define OP_OP_COP0 0x10 171 #define OP_OP_COP1 0x11 172 #define OP_OP_COP2 0x12 173 #define OP_OP_COP3 0x13 174 #define OP_OP_LWC1 0x31 175 #define OP_OP_LWC2 0x32 176 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 177 #define OP_OP_LDC1 0x35 178 #define OP_OP_LDC2 0x36 179 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 180 #define OP_OP_SWC1 0x39 181 #define OP_OP_SWC2 0x3a 182 #define OP_OP_SWC3 0x3b 183 #define OP_OP_SDC1 0x3d 184 #define OP_OP_SDC2 0x3e 185 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 186 187 /* MIPS DSP ASE */ 188 #define OP_SH_DSPACC 11 189 #define OP_MASK_DSPACC 0x3 190 #define OP_SH_DSPACC_S 21 191 #define OP_MASK_DSPACC_S 0x3 192 #define OP_SH_DSPSFT 20 193 #define OP_MASK_DSPSFT 0x3f 194 #define OP_SH_DSPSFT_7 19 195 #define OP_MASK_DSPSFT_7 0x7f 196 #define OP_SH_SA3 21 197 #define OP_MASK_SA3 0x7 198 #define OP_SH_SA4 21 199 #define OP_MASK_SA4 0xf 200 #define OP_SH_IMM8 16 201 #define OP_MASK_IMM8 0xff 202 #define OP_SH_IMM10 16 203 #define OP_MASK_IMM10 0x3ff 204 #define OP_SH_WRDSP 11 205 #define OP_MASK_WRDSP 0x3f 206 #define OP_SH_RDDSP 16 207 #define OP_MASK_RDDSP 0x3f 208 #define OP_SH_BP 11 209 #define OP_MASK_BP 0x3 210 211 /* MIPS MT ASE */ 212 #define OP_SH_MT_U 5 213 #define OP_MASK_MT_U 0x1 214 #define OP_SH_MT_H 4 215 #define OP_MASK_MT_H 0x1 216 #define OP_SH_MTACC_T 18 217 #define OP_MASK_MTACC_T 0x3 218 #define OP_SH_MTACC_D 13 219 #define OP_MASK_MTACC_D 0x3 220 221 #define OP_OP_COP0 0x10 222 #define OP_OP_COP1 0x11 223 #define OP_OP_COP2 0x12 224 #define OP_OP_COP3 0x13 225 #define OP_OP_LWC1 0x31 226 #define OP_OP_LWC2 0x32 227 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 228 #define OP_OP_LDC1 0x35 229 #define OP_OP_LDC2 0x36 230 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 231 #define OP_OP_SWC1 0x39 232 #define OP_OP_SWC2 0x3a 233 #define OP_OP_SWC3 0x3b 234 #define OP_OP_SDC1 0x3d 235 #define OP_OP_SDC2 0x3e 236 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 237 238 /* Values in the 'VSEL' field. */ 239 #define MDMX_FMTSEL_IMM_QH 0x1d 240 #define MDMX_FMTSEL_IMM_OB 0x1e 241 #define MDMX_FMTSEL_VEC_QH 0x15 242 #define MDMX_FMTSEL_VEC_OB 0x16 243 244 /* UDI */ 245 #define OP_SH_UDI1 6 246 #define OP_MASK_UDI1 0x1f 247 #define OP_SH_UDI2 6 248 #define OP_MASK_UDI2 0x3ff 249 #define OP_SH_UDI3 6 250 #define OP_MASK_UDI3 0x7fff 251 #define OP_SH_UDI4 6 252 #define OP_MASK_UDI4 0xfffff 253 /* This structure holds information for a particular instruction. */ 254 255 struct mips_opcode 256 { 257 /* The name of the instruction. */ 258 const char *name; 259 /* A string describing the arguments for this instruction. */ 260 const char *args; 261 /* The basic opcode for the instruction. When assembling, this 262 opcode is modified by the arguments to produce the actual opcode 263 that is used. If pinfo is INSN_MACRO, then this is 0. */ 264 unsigned long match; 265 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 266 relevant portions of the opcode when disassembling. If the 267 actual opcode anded with the match field equals the opcode field, 268 then we have found the correct instruction. If pinfo is 269 INSN_MACRO, then this field is the macro identifier. */ 270 unsigned long mask; 271 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 272 of bits describing the instruction, notably any relevant hazard 273 information. */ 274 unsigned long pinfo; 275 /* A collection of additional bits describing the instruction. */ 276 unsigned long pinfo2; 277 /* A collection of bits describing the instruction sets of which this 278 instruction or macro is a member. */ 279 unsigned long membership; 280 }; 281 282 /* These are the characters which may appear in the args field of an 283 instruction. They appear in the order in which the fields appear 284 when the instruction is used. Commas and parentheses in the args 285 string are ignored when assembling, and written into the output 286 when disassembling. 287 288 Each of these characters corresponds to a mask field defined above. 289 290 "<" 5 bit shift amount (OP_*_SHAMT) 291 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 292 "a" 26 bit target address (OP_*_TARGET) 293 "b" 5 bit base register (OP_*_RS) 294 "c" 10 bit breakpoint code (OP_*_CODE) 295 "d" 5 bit destination register specifier (OP_*_RD) 296 "h" 5 bit prefx hint (OP_*_PREFX) 297 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 298 "j" 16 bit signed immediate (OP_*_DELTA) 299 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 300 Also used for immediate operands in vr5400 vector insns. 301 "o" 16 bit signed offset (OP_*_DELTA) 302 "p" 16 bit PC relative branch target address (OP_*_DELTA) 303 "q" 10 bit extra breakpoint code (OP_*_CODE2) 304 "r" 5 bit same register used as both source and target (OP_*_RS) 305 "s" 5 bit source register specifier (OP_*_RS) 306 "t" 5 bit target register (OP_*_RT) 307 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 308 "v" 5 bit same register used as both source and destination (OP_*_RS) 309 "w" 5 bit same register used as both target and destination (OP_*_RT) 310 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 311 (used by clo and clz) 312 "C" 25 bit coprocessor function code (OP_*_COPZ) 313 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 314 "J" 19 bit wait function code (OP_*_CODE19) 315 "x" accept and ignore register name 316 "z" must be zero register 317 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 318 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 319 LSB (OP_*_SHAMT). 320 Enforces: 0 <= pos < 32. 321 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 322 Requires that "+A" or "+E" occur first to set position. 323 Enforces: 0 < (pos+size) <= 32. 324 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 325 Requires that "+A" or "+E" occur first to set position. 326 Enforces: 0 < (pos+size) <= 32. 327 (Also used by "dext" w/ different limits, but limits for 328 that are checked by the M_DEXT macro.) 329 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 330 Enforces: 32 <= pos < 64. 331 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 332 Requires that "+A" or "+E" occur first to set position. 333 Enforces: 32 < (pos+size) <= 64. 334 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 335 Requires that "+A" or "+E" occur first to set position. 336 Enforces: 32 < (pos+size) <= 64. 337 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 338 Requires that "+A" or "+E" occur first to set position. 339 Enforces: 32 < (pos+size) <= 64. 340 341 Floating point instructions: 342 "D" 5 bit destination register (OP_*_FD) 343 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 344 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 345 "S" 5 bit fs source 1 register (OP_*_FS) 346 "T" 5 bit ft source 2 register (OP_*_FT) 347 "R" 5 bit fr source 3 register (OP_*_FR) 348 "V" 5 bit same register used as floating source and destination (OP_*_FS) 349 "W" 5 bit same register used as floating target and destination (OP_*_FT) 350 351 Coprocessor instructions: 352 "E" 5 bit target register (OP_*_RT) 353 "G" 5 bit destination register (OP_*_RD) 354 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 355 "P" 5 bit performance-monitor register (OP_*_PERFREG) 356 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 357 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 358 see also "k" above 359 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 360 for pretty-printing in disassembly only. 361 362 Macro instructions: 363 "A" General 32 bit expression 364 "I" 32 bit immediate (value placed in imm_expr). 365 "+I" 32 bit immediate (value placed in imm2_expr). 366 "F" 64 bit floating point constant in .rdata 367 "L" 64 bit floating point constant in .lit8 368 "f" 32 bit floating point constant 369 "l" 32 bit floating point constant in .lit4 370 371 MDMX instruction operands (note that while these use the FP register 372 fields, they accept both $fN and $vN names for the registers): 373 "O" MDMX alignment offset (OP_*_ALN) 374 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 375 "X" MDMX destination register (OP_*_FD) 376 "Y" MDMX source register (OP_*_FS) 377 "Z" MDMX source register (OP_*_FT) 378 379 DSP ASE usage: 380 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 381 "3" 3 bit unsigned immediate (OP_*_SA3) 382 "4" 4 bit unsigned immediate (OP_*_SA4) 383 "5" 8 bit unsigned immediate (OP_*_IMM8) 384 "6" 5 bit unsigned immediate (OP_*_RS) 385 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 386 "8" 6 bit unsigned immediate (OP_*_WRDSP) 387 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 388 "0" 6 bit signed immediate (OP_*_DSPSFT) 389 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 390 "'" 6 bit unsigned immediate (OP_*_RDDSP) 391 "@" 10 bit signed immediate (OP_*_IMM10) 392 393 MT ASE usage: 394 "!" 1 bit usermode flag (OP_*_MT_U) 395 "$" 1 bit load high flag (OP_*_MT_H) 396 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 397 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 398 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 399 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 400 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 401 402 UDI immediates: 403 "+1" UDI immediate bits 6-10 404 "+2" UDI immediate bits 6-15 405 "+3" UDI immediate bits 6-20 406 "+4" UDI immediate bits 6-25 407 408 Other: 409 "()" parens surrounding optional value 410 "," separates operands 411 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 412 "+" Start of extension sequence. 413 414 Characters used so far, for quick reference when adding more: 415 "234567890" 416 "%[]<>(),+:'@!$*&" 417 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 418 "abcdefghijklopqrstuvwxz" 419 420 Extension character sequences used so far ("+" followed by the 421 following), for quick reference when adding more: 422 "1234" 423 "ABCDEFGHIT" 424 "t" 425 */ 426 427 /* These are the bits which may be set in the pinfo field of an 428 instructions, if it is not equal to INSN_MACRO. */ 429 430 /* Modifies the general purpose register in OP_*_RD. */ 431 #define INSN_WRITE_GPR_D 0x00000001 432 /* Modifies the general purpose register in OP_*_RT. */ 433 #define INSN_WRITE_GPR_T 0x00000002 434 /* Modifies general purpose register 31. */ 435 #define INSN_WRITE_GPR_31 0x00000004 436 /* Modifies the floating point register in OP_*_FD. */ 437 #define INSN_WRITE_FPR_D 0x00000008 438 /* Modifies the floating point register in OP_*_FS. */ 439 #define INSN_WRITE_FPR_S 0x00000010 440 /* Modifies the floating point register in OP_*_FT. */ 441 #define INSN_WRITE_FPR_T 0x00000020 442 /* Reads the general purpose register in OP_*_RS. */ 443 #define INSN_READ_GPR_S 0x00000040 444 /* Reads the general purpose register in OP_*_RT. */ 445 #define INSN_READ_GPR_T 0x00000080 446 /* Reads the floating point register in OP_*_FS. */ 447 #define INSN_READ_FPR_S 0x00000100 448 /* Reads the floating point register in OP_*_FT. */ 449 #define INSN_READ_FPR_T 0x00000200 450 /* Reads the floating point register in OP_*_FR. */ 451 #define INSN_READ_FPR_R 0x00000400 452 /* Modifies coprocessor condition code. */ 453 #define INSN_WRITE_COND_CODE 0x00000800 454 /* Reads coprocessor condition code. */ 455 #define INSN_READ_COND_CODE 0x00001000 456 /* TLB operation. */ 457 #define INSN_TLB 0x00002000 458 /* Reads coprocessor register other than floating point register. */ 459 #define INSN_COP 0x00004000 460 /* Instruction loads value from memory, requiring delay. */ 461 #define INSN_LOAD_MEMORY_DELAY 0x00008000 462 /* Instruction loads value from coprocessor, requiring delay. */ 463 #define INSN_LOAD_COPROC_DELAY 0x00010000 464 /* Instruction has unconditional branch delay slot. */ 465 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 466 /* Instruction has conditional branch delay slot. */ 467 #define INSN_COND_BRANCH_DELAY 0x00040000 468 /* Conditional branch likely: if branch not taken, insn nullified. */ 469 #define INSN_COND_BRANCH_LIKELY 0x00080000 470 /* Moves to coprocessor register, requiring delay. */ 471 #define INSN_COPROC_MOVE_DELAY 0x00100000 472 /* Loads coprocessor register from memory, requiring delay. */ 473 #define INSN_COPROC_MEMORY_DELAY 0x00200000 474 /* Reads the HI register. */ 475 #define INSN_READ_HI 0x00400000 476 /* Reads the LO register. */ 477 #define INSN_READ_LO 0x00800000 478 /* Modifies the HI register. */ 479 #define INSN_WRITE_HI 0x01000000 480 /* Modifies the LO register. */ 481 #define INSN_WRITE_LO 0x02000000 482 /* Takes a trap (easier to keep out of delay slot). */ 483 #define INSN_TRAP 0x04000000 484 /* Instruction stores value into memory. */ 485 #define INSN_STORE_MEMORY 0x08000000 486 /* Instruction uses single precision floating point. */ 487 #define FP_S 0x10000000 488 /* Instruction uses double precision floating point. */ 489 #define FP_D 0x20000000 490 /* Instruction is part of the tx39's integer multiply family. */ 491 #define INSN_MULT 0x40000000 492 /* Instruction synchronize shared memory. */ 493 #define INSN_SYNC 0x80000000 494 495 /* These are the bits which may be set in the pinfo2 field of an 496 instruction. */ 497 498 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 499 #define INSN2_ALIAS 0x00000001 500 /* Instruction reads MDMX accumulator. */ 501 #define INSN2_READ_MDMX_ACC 0x00000002 502 /* Instruction writes MDMX accumulator. */ 503 #define INSN2_WRITE_MDMX_ACC 0x00000004 504 505 /* Instruction is actually a macro. It should be ignored by the 506 disassembler, and requires special treatment by the assembler. */ 507 #define INSN_MACRO 0xffffffff 508 509 /* Masks used to mark instructions to indicate which MIPS ISA level 510 they were introduced in. ISAs, as defined below, are logical 511 ORs of these bits, indicating that they support the instructions 512 defined at the given level. */ 513 514 #define INSN_ISA_MASK 0x00000fff 515 #define INSN_ISA1 0x00000001 516 #define INSN_ISA2 0x00000002 517 #define INSN_ISA3 0x00000004 518 #define INSN_ISA4 0x00000008 519 #define INSN_ISA5 0x00000010 520 #define INSN_ISA32 0x00000020 521 #define INSN_ISA64 0x00000040 522 #define INSN_ISA32R2 0x00000080 523 #define INSN_ISA64R2 0x00000100 524 525 /* Masks used for MIPS-defined ASEs. */ 526 #define INSN_ASE_MASK 0x0000f000 527 528 /* DSP ASE */ 529 #define INSN_DSP 0x00001000 530 #define INSN_DSP64 0x00002000 531 /* MIPS 16 ASE */ 532 #define INSN_MIPS16 0x00004000 533 /* MIPS-3D ASE */ 534 #define INSN_MIPS3D 0x00008000 535 536 /* Chip specific instructions. These are bitmasks. */ 537 538 /* MIPS R4650 instruction. */ 539 #define INSN_4650 0x00010000 540 /* LSI R4010 instruction. */ 541 #define INSN_4010 0x00020000 542 /* NEC VR4100 instruction. */ 543 #define INSN_4100 0x00040000 544 /* Toshiba R3900 instruction. */ 545 #define INSN_3900 0x00080000 546 /* MIPS R10000 instruction. */ 547 #define INSN_10000 0x00100000 548 /* Broadcom SB-1 instruction. */ 549 #define INSN_SB1 0x00200000 550 /* NEC VR4111/VR4181 instruction. */ 551 #define INSN_4111 0x00400000 552 /* NEC VR4120 instruction. */ 553 #define INSN_4120 0x00800000 554 /* NEC VR5400 instruction. */ 555 #define INSN_5400 0x01000000 556 /* NEC VR5500 instruction. */ 557 #define INSN_5500 0x02000000 558 559 /* MDMX ASE */ 560 #define INSN_MDMX 0x04000000 561 /* MT ASE */ 562 #define INSN_MT 0x08000000 563 /* SmartMIPS ASE */ 564 #define INSN_SMARTMIPS 0x10000000 565 /* DSP R2 ASE */ 566 #define INSN_DSPR2 0x20000000 567 568 /* ST Microelectronics Loongson 2E. */ 569 #define INSN_LOONGSON_2E 0x40000000 570 /* ST Microelectronics Loongson 2F. */ 571 #define INSN_LOONGSON_2F 0x80000000 572 573 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 574 575 #ifndef ISA_MIPS1 576 #define ISA_UNKNOWN 0 /* Gas internal use. */ 577 #define ISA_MIPS1 (INSN_ISA1) 578 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 579 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 580 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 581 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 582 583 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 584 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 585 586 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 587 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 588 #endif // ISA_MIPS1 589 590 /* CPU defines, use instead of hardcoding processor number. Keep this 591 in sync with bfd/archures.c in order for machine selection to work. */ 592 #define CPU_UNKNOWN 0 /* Gas internal use. */ 593 #define CPU_R3000 3000 594 #define CPU_R3900 3900 595 #define CPU_R4000 4000 596 #define CPU_R4010 4010 597 #define CPU_VR4100 4100 598 #define CPU_R4111 4111 599 #define CPU_VR4120 4120 600 #define CPU_R4300 4300 601 #define CPU_R4400 4400 602 #define CPU_R4600 4600 603 #define CPU_R4650 4650 604 #define CPU_R5000 5000 605 #define CPU_VR5400 5400 606 #define CPU_VR5500 5500 607 #define CPU_R6000 6000 608 #define CPU_RM7000 7000 609 #define CPU_R8000 8000 610 #define CPU_R10000 10000 611 #define CPU_R12000 12000 612 613 #define CPU_MIPS16 16 614 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 615 616 #ifndef CPU_MIPS32 617 #define CPU_MIPS32 32 618 #define CPU_MIPS32R2 33 619 #define CPU_MIPS5 5 620 #define CPU_MIPS64 64 621 #define CPU_MIPS64R2 65 622 #endif // !CPU_MIPS32 623 624 /* Test for membership in an ISA including chip specific ISAs. INSN 625 is pointer to an element of the opcode table; ISA is the specified 626 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 627 test, or zero if no CPU specific ISA test is desired. */ 628 629 #if 0 630 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 631 (((insn)->membership & isa) != 0 \ 632 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 633 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 634 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 635 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 636 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 637 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 638 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 639 && ((insn)->membership & INSN_10000) != 0) \ 640 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 641 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 642 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 643 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 644 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 645 || 0) /* Please keep this term for easier source merging. */ 646 #else 647 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 648 (1 != 0) 649 #endif 650 651 /* This is a list of macro expanded instructions. 652 653 _I appended means immediate 654 _A appended means address 655 _AB appended means address with base register 656 _D appended means 64 bit floating point constant 657 _S appended means 32 bit floating point constant. */ 658 659 enum 660 { 661 M_ABS, 662 M_ADD_I, 663 M_ADDU_I, 664 M_AND_I, 665 M_BALIGN, 666 M_BEQ, 667 M_BEQ_I, 668 M_BEQL_I, 669 M_BGE, 670 M_BGEL, 671 M_BGE_I, 672 M_BGEL_I, 673 M_BGEU, 674 M_BGEUL, 675 M_BGEU_I, 676 M_BGEUL_I, 677 M_BGT, 678 M_BGTL, 679 M_BGT_I, 680 M_BGTL_I, 681 M_BGTU, 682 M_BGTUL, 683 M_BGTU_I, 684 M_BGTUL_I, 685 M_BLE, 686 M_BLEL, 687 M_BLE_I, 688 M_BLEL_I, 689 M_BLEU, 690 M_BLEUL, 691 M_BLEU_I, 692 M_BLEUL_I, 693 M_BLT, 694 M_BLTL, 695 M_BLT_I, 696 M_BLTL_I, 697 M_BLTU, 698 M_BLTUL, 699 M_BLTU_I, 700 M_BLTUL_I, 701 M_BNE, 702 M_BNE_I, 703 M_BNEL_I, 704 M_CACHE_AB, 705 M_DABS, 706 M_DADD_I, 707 M_DADDU_I, 708 M_DDIV_3, 709 M_DDIV_3I, 710 M_DDIVU_3, 711 M_DDIVU_3I, 712 M_DEXT, 713 M_DINS, 714 M_DIV_3, 715 M_DIV_3I, 716 M_DIVU_3, 717 M_DIVU_3I, 718 M_DLA_AB, 719 M_DLCA_AB, 720 M_DLI, 721 M_DMUL, 722 M_DMUL_I, 723 M_DMULO, 724 M_DMULO_I, 725 M_DMULOU, 726 M_DMULOU_I, 727 M_DREM_3, 728 M_DREM_3I, 729 M_DREMU_3, 730 M_DREMU_3I, 731 M_DSUB_I, 732 M_DSUBU_I, 733 M_DSUBU_I_2, 734 M_J_A, 735 M_JAL_1, 736 M_JAL_2, 737 M_JAL_A, 738 M_L_DOB, 739 M_L_DAB, 740 M_LA_AB, 741 M_LB_A, 742 M_LB_AB, 743 M_LBU_A, 744 M_LBU_AB, 745 M_LCA_AB, 746 M_LD_A, 747 M_LD_OB, 748 M_LD_AB, 749 M_LDC1_AB, 750 M_LDC2_AB, 751 M_LDC3_AB, 752 M_LDL_AB, 753 M_LDR_AB, 754 M_LH_A, 755 M_LH_AB, 756 M_LHU_A, 757 M_LHU_AB, 758 M_LI, 759 M_LI_D, 760 M_LI_DD, 761 M_LI_S, 762 M_LI_SS, 763 M_LL_AB, 764 M_LLD_AB, 765 M_LS_A, 766 M_LW_A, 767 M_LW_AB, 768 M_LWC0_A, 769 M_LWC0_AB, 770 M_LWC1_A, 771 M_LWC1_AB, 772 M_LWC2_A, 773 M_LWC2_AB, 774 M_LWC3_A, 775 M_LWC3_AB, 776 M_LWL_A, 777 M_LWL_AB, 778 M_LWR_A, 779 M_LWR_AB, 780 M_LWU_AB, 781 M_MOVE, 782 M_MUL, 783 M_MUL_I, 784 M_MULO, 785 M_MULO_I, 786 M_MULOU, 787 M_MULOU_I, 788 M_NOR_I, 789 M_OR_I, 790 M_REM_3, 791 M_REM_3I, 792 M_REMU_3, 793 M_REMU_3I, 794 M_DROL, 795 M_ROL, 796 M_DROL_I, 797 M_ROL_I, 798 M_DROR, 799 M_ROR, 800 M_DROR_I, 801 M_ROR_I, 802 M_S_DA, 803 M_S_DOB, 804 M_S_DAB, 805 M_S_S, 806 M_SC_AB, 807 M_SCD_AB, 808 M_SD_A, 809 M_SD_OB, 810 M_SD_AB, 811 M_SDC1_AB, 812 M_SDC2_AB, 813 M_SDC3_AB, 814 M_SDL_AB, 815 M_SDR_AB, 816 M_SEQ, 817 M_SEQ_I, 818 M_SGE, 819 M_SGE_I, 820 M_SGEU, 821 M_SGEU_I, 822 M_SGT, 823 M_SGT_I, 824 M_SGTU, 825 M_SGTU_I, 826 M_SLE, 827 M_SLE_I, 828 M_SLEU, 829 M_SLEU_I, 830 M_SLT_I, 831 M_SLTU_I, 832 M_SNE, 833 M_SNE_I, 834 M_SB_A, 835 M_SB_AB, 836 M_SH_A, 837 M_SH_AB, 838 M_SW_A, 839 M_SW_AB, 840 M_SWC0_A, 841 M_SWC0_AB, 842 M_SWC1_A, 843 M_SWC1_AB, 844 M_SWC2_A, 845 M_SWC2_AB, 846 M_SWC3_A, 847 M_SWC3_AB, 848 M_SWL_A, 849 M_SWL_AB, 850 M_SWR_A, 851 M_SWR_AB, 852 M_SUB_I, 853 M_SUBU_I, 854 M_SUBU_I_2, 855 M_TEQ_I, 856 M_TGE_I, 857 M_TGEU_I, 858 M_TLT_I, 859 M_TLTU_I, 860 M_TNE_I, 861 M_TRUNCWD, 862 M_TRUNCWS, 863 M_ULD, 864 M_ULD_A, 865 M_ULH, 866 M_ULH_A, 867 M_ULHU, 868 M_ULHU_A, 869 M_ULW, 870 M_ULW_A, 871 M_USH, 872 M_USH_A, 873 M_USW, 874 M_USW_A, 875 M_USD, 876 M_USD_A, 877 M_XOR_I, 878 M_COP0, 879 M_COP1, 880 M_COP2, 881 M_COP3, 882 M_NUM_MACROS 883 }; 884 885 886 /* The order of overloaded instructions matters. Label arguments and 887 register arguments look the same. Instructions that can have either 888 for arguments must apear in the correct order in this table for the 889 assembler to pick the right one. In other words, entries with 890 immediate operands must apear after the same instruction with 891 registers. 892 893 Many instructions are short hand for other instructions (i.e., The 894 jal <register> instruction is short for jalr <register>). */ 895 896 extern const struct mips_opcode mips_builtin_opcodes[]; 897 extern const int bfd_mips_num_builtin_opcodes; 898 extern struct mips_opcode *mips_opcodes; 899 extern int bfd_mips_num_opcodes; 900 #define NUMOPCODES bfd_mips_num_opcodes 901 902 903 /* The rest of this file adds definitions for the mips16 TinyRISC 905 processor. */ 906 907 /* These are the bitmasks and shift counts used for the different 908 fields in the instruction formats. Other than OP, no masks are 909 provided for the fixed portions of an instruction, since they are 910 not needed. 911 912 The I format uses IMM11. 913 914 The RI format uses RX and IMM8. 915 916 The RR format uses RX, and RY. 917 918 The RRI format uses RX, RY, and IMM5. 919 920 The RRR format uses RX, RY, and RZ. 921 922 The RRI_A format uses RX, RY, and IMM4. 923 924 The SHIFT format uses RX, RY, and SHAMT. 925 926 The I8 format uses IMM8. 927 928 The I8_MOVR32 format uses RY and REGR32. 929 930 The IR_MOV32R format uses REG32R and MOV32Z. 931 932 The I64 format uses IMM8. 933 934 The RI64 format uses RY and IMM5. 935 */ 936 937 #define MIPS16OP_MASK_OP 0x1f 938 #define MIPS16OP_SH_OP 11 939 #define MIPS16OP_MASK_IMM11 0x7ff 940 #define MIPS16OP_SH_IMM11 0 941 #define MIPS16OP_MASK_RX 0x7 942 #define MIPS16OP_SH_RX 8 943 #define MIPS16OP_MASK_IMM8 0xff 944 #define MIPS16OP_SH_IMM8 0 945 #define MIPS16OP_MASK_RY 0x7 946 #define MIPS16OP_SH_RY 5 947 #define MIPS16OP_MASK_IMM5 0x1f 948 #define MIPS16OP_SH_IMM5 0 949 #define MIPS16OP_MASK_RZ 0x7 950 #define MIPS16OP_SH_RZ 2 951 #define MIPS16OP_MASK_IMM4 0xf 952 #define MIPS16OP_SH_IMM4 0 953 #define MIPS16OP_MASK_REGR32 0x1f 954 #define MIPS16OP_SH_REGR32 0 955 #define MIPS16OP_MASK_REG32R 0x1f 956 #define MIPS16OP_SH_REG32R 3 957 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 958 #define MIPS16OP_MASK_MOVE32Z 0x7 959 #define MIPS16OP_SH_MOVE32Z 0 960 #define MIPS16OP_MASK_IMM6 0x3f 961 #define MIPS16OP_SH_IMM6 5 962 963 /* These are the characters which may appears in the args field of an 964 instruction. They appear in the order in which the fields appear 965 when the instruction is used. Commas and parentheses in the args 966 string are ignored when assembling, and written into the output 967 when disassembling. 968 969 "y" 3 bit register (MIPS16OP_*_RY) 970 "x" 3 bit register (MIPS16OP_*_RX) 971 "z" 3 bit register (MIPS16OP_*_RZ) 972 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 973 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 974 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 975 "0" zero register ($0) 976 "S" stack pointer ($sp or $29) 977 "P" program counter 978 "R" return address register ($ra or $31) 979 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 980 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 981 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 982 "a" 26 bit jump address 983 "e" 11 bit extension value 984 "l" register list for entry instruction 985 "L" register list for exit instruction 986 987 The remaining codes may be extended. Except as otherwise noted, 988 the full extended operand is a 16 bit signed value. 989 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 990 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 991 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 992 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 993 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 994 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 995 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 996 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 997 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 998 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 999 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1000 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1001 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1002 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1003 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1004 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1005 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1006 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1007 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1008 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1009 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1010 */ 1011 1012 /* Save/restore encoding for the args field when all 4 registers are 1013 either saved as arguments or saved/restored as statics. */ 1014 #define MIPS16_ALL_ARGS 0xe 1015 #define MIPS16_ALL_STATICS 0xb 1016 1017 /* For the mips16, we use the same opcode table format and a few of 1018 the same flags. However, most of the flags are different. */ 1019 1020 /* Modifies the register in MIPS16OP_*_RX. */ 1021 #define MIPS16_INSN_WRITE_X 0x00000001 1022 /* Modifies the register in MIPS16OP_*_RY. */ 1023 #define MIPS16_INSN_WRITE_Y 0x00000002 1024 /* Modifies the register in MIPS16OP_*_RZ. */ 1025 #define MIPS16_INSN_WRITE_Z 0x00000004 1026 /* Modifies the T ($24) register. */ 1027 #define MIPS16_INSN_WRITE_T 0x00000008 1028 /* Modifies the SP ($29) register. */ 1029 #define MIPS16_INSN_WRITE_SP 0x00000010 1030 /* Modifies the RA ($31) register. */ 1031 #define MIPS16_INSN_WRITE_31 0x00000020 1032 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 1033 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 1034 /* Reads the register in MIPS16OP_*_RX. */ 1035 #define MIPS16_INSN_READ_X 0x00000080 1036 /* Reads the register in MIPS16OP_*_RY. */ 1037 #define MIPS16_INSN_READ_Y 0x00000100 1038 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 1039 #define MIPS16_INSN_READ_Z 0x00000200 1040 /* Reads the T ($24) register. */ 1041 #define MIPS16_INSN_READ_T 0x00000400 1042 /* Reads the SP ($29) register. */ 1043 #define MIPS16_INSN_READ_SP 0x00000800 1044 /* Reads the RA ($31) register. */ 1045 #define MIPS16_INSN_READ_31 0x00001000 1046 /* Reads the program counter. */ 1047 #define MIPS16_INSN_READ_PC 0x00002000 1048 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1049 #define MIPS16_INSN_READ_GPR_X 0x00004000 1050 /* Is a branch insn. */ 1051 #define MIPS16_INSN_BRANCH 0x00010000 1052 1053 /* The following flags have the same value for the mips16 opcode 1054 table: 1055 INSN_UNCOND_BRANCH_DELAY 1056 INSN_COND_BRANCH_DELAY 1057 INSN_COND_BRANCH_LIKELY (never used) 1058 INSN_READ_HI 1059 INSN_READ_LO 1060 INSN_WRITE_HI 1061 INSN_WRITE_LO 1062 INSN_TRAP 1063 INSN_ISA3 1064 */ 1065 1066 extern const struct mips_opcode mips16_opcodes[]; 1067 extern const int bfd_mips16_num_opcodes; 1068 1069 /* Short hand so the lines aren't too long. */ 1070 1071 #define LDD INSN_LOAD_MEMORY_DELAY 1072 #define LCD INSN_LOAD_COPROC_DELAY 1073 #define UBD INSN_UNCOND_BRANCH_DELAY 1074 #define CBD INSN_COND_BRANCH_DELAY 1075 #define COD INSN_COPROC_MOVE_DELAY 1076 #define CLD INSN_COPROC_MEMORY_DELAY 1077 #define CBL INSN_COND_BRANCH_LIKELY 1078 #define TRAP INSN_TRAP 1079 #define SM INSN_STORE_MEMORY 1080 1081 #define WR_d INSN_WRITE_GPR_D 1082 #define WR_t INSN_WRITE_GPR_T 1083 #define WR_31 INSN_WRITE_GPR_31 1084 #define WR_D INSN_WRITE_FPR_D 1085 #define WR_T INSN_WRITE_FPR_T 1086 #define WR_S INSN_WRITE_FPR_S 1087 #define RD_s INSN_READ_GPR_S 1088 #define RD_b INSN_READ_GPR_S 1089 #define RD_t INSN_READ_GPR_T 1090 #define RD_S INSN_READ_FPR_S 1091 #define RD_T INSN_READ_FPR_T 1092 #define RD_R INSN_READ_FPR_R 1093 #define WR_CC INSN_WRITE_COND_CODE 1094 #define RD_CC INSN_READ_COND_CODE 1095 #define RD_C0 INSN_COP 1096 #define RD_C1 INSN_COP 1097 #define RD_C2 INSN_COP 1098 #define RD_C3 INSN_COP 1099 #define WR_C0 INSN_COP 1100 #define WR_C1 INSN_COP 1101 #define WR_C2 INSN_COP 1102 #define WR_C3 INSN_COP 1103 1104 #define WR_HI INSN_WRITE_HI 1105 #define RD_HI INSN_READ_HI 1106 #define MOD_HI WR_HI|RD_HI 1107 1108 #define WR_LO INSN_WRITE_LO 1109 #define RD_LO INSN_READ_LO 1110 #define MOD_LO WR_LO|RD_LO 1111 1112 #define WR_HILO WR_HI|WR_LO 1113 #define RD_HILO RD_HI|RD_LO 1114 #define MOD_HILO WR_HILO|RD_HILO 1115 1116 #define IS_M INSN_MULT 1117 1118 #define WR_MACC INSN2_WRITE_MDMX_ACC 1119 #define RD_MACC INSN2_READ_MDMX_ACC 1120 1121 #define I1 INSN_ISA1 1122 #define I2 INSN_ISA2 1123 #define I3 INSN_ISA3 1124 #define I4 INSN_ISA4 1125 #define I5 INSN_ISA5 1126 #define I32 INSN_ISA32 1127 #define I64 INSN_ISA64 1128 #define I33 INSN_ISA32R2 1129 #define I65 INSN_ISA64R2 1130 1131 /* MIPS64 MIPS-3D ASE support. */ 1132 #define I16 INSN_MIPS16 1133 1134 /* MIPS32 SmartMIPS ASE support. */ 1135 #define SMT INSN_SMARTMIPS 1136 1137 /* MIPS64 MIPS-3D ASE support. */ 1138 #define M3D INSN_MIPS3D 1139 1140 /* MIPS64 MDMX ASE support. */ 1141 #define MX INSN_MDMX 1142 1143 #define IL2E (INSN_LOONGSON_2E) 1144 #define IL2F (INSN_LOONGSON_2F) 1145 1146 #define P3 INSN_4650 1147 #define L1 INSN_4010 1148 #define V1 (INSN_4100 | INSN_4111 | INSN_4120) 1149 #define T3 INSN_3900 1150 #define M1 INSN_10000 1151 #define SB1 INSN_SB1 1152 #define N411 INSN_4111 1153 #define N412 INSN_4120 1154 #define N5 (INSN_5400 | INSN_5500) 1155 #define N54 INSN_5400 1156 #define N55 INSN_5500 1157 1158 #define G1 (T3 \ 1159 ) 1160 1161 #define G2 (T3 \ 1162 ) 1163 1164 #define G3 (I4 \ 1165 ) 1166 1167 /* MIPS DSP ASE support. 1168 NOTE: 1169 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair 1170 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have 1171 the same structure as $ac0 (HI + LO). For DSP instructions that write or 1172 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a 1173 (RD_HILO) attributes, such that HILO dependencies are maintained 1174 conservatively. 1175 1176 2. For some mul. instructions that use integer registers as destinations 1177 but destroy HI+LO as side-effect, we add WR_HILO to their attributes. 1178 1179 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields 1180 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write 1181 certain fields of the DSP control register. For simplicity, we decide not 1182 to track dependencies of these fields. 1183 However, "bposge32" is a branch instruction that depends on the "pos" 1184 field. In order to make sure that GAS does not reorder DSP instructions 1185 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) 1186 attribute to those instructions that write the "pos" field. */ 1187 1188 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ 1189 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ 1190 #define MOD_a WR_a|RD_a 1191 #define DSP_VOLA INSN_TRAP 1192 #define D32 INSN_DSP 1193 #define D33 INSN_DSPR2 1194 #define D64 INSN_DSP64 1195 1196 /* MIPS MT ASE support. */ 1197 #define MT32 INSN_MT 1198 1199 /* The order of overloaded instructions matters. Label arguments and 1200 register arguments look the same. Instructions that can have either 1201 for arguments must apear in the correct order in this table for the 1202 assembler to pick the right one. In other words, entries with 1203 immediate operands must apear after the same instruction with 1204 registers. 1205 1206 Because of the lookup algorithm used, entries with the same opcode 1207 name must be contiguous. 1208 1209 Many instructions are short hand for other instructions (i.e., The 1210 jal <register> instruction is short for jalr <register>). */ 1211 1212 const struct mips_opcode mips_builtin_opcodes[] = 1213 { 1214 /* These instructions appear first so that the disassembler will find 1215 them first. The assemblers uses a hash table based on the 1216 instruction name anyhow. */ 1217 /* name, args, match, mask, pinfo, membership */ 1218 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, 1219 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, 1220 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ 1221 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ 1222 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ 1223 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ 1224 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ 1225 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, 1226 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, 1227 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ 1228 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ 1229 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ 1230 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ 1231 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ 1232 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ 1233 1234 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, 1235 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1236 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1237 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1238 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1239 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, 1240 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1241 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1242 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1243 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1244 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1245 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1246 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1247 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1248 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1249 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1250 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1251 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1252 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1253 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1254 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1255 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1256 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, 1257 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1258 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, 1259 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1260 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1261 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, 1262 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, 1263 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1264 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, 1265 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1266 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1267 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1268 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1269 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1270 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1271 /* b is at the top of the table. */ 1272 /* bal is at the top of the table. */ 1273 /* bc0[tf]l? are at the bottom of the table. */ 1274 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1275 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1276 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1277 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 1278 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1279 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1280 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1281 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1282 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 1283 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 1284 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1285 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 1286 /* bc2* are at the bottom of the table. */ 1287 /* bc3* are at the bottom of the table. */ 1288 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1289 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1290 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1291 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, 1292 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1293 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, 1294 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, 1295 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, 1296 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, 1297 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, 1298 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, 1299 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, 1300 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, 1301 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, 1302 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1303 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1304 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1305 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1306 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, 1307 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, 1308 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, 1309 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, 1310 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, 1311 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, 1312 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, 1313 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, 1314 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1315 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1316 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, 1317 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, 1318 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, 1319 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, 1320 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, 1321 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, 1322 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, 1323 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, 1324 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1325 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1326 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, 1327 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, 1328 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, 1329 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, 1330 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, 1331 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, 1332 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, 1333 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, 1334 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1335 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1336 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 1337 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 1338 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 1339 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1340 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 1341 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, 1342 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1343 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, 1344 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, 1345 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, 1346 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, 1347 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1348 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1349 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1350 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1351 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1352 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1353 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1354 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1355 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1356 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1357 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1358 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1359 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1360 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1361 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1362 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1363 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1364 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1365 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1366 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1367 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1368 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1369 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1370 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1371 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1372 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1373 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1374 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1375 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1376 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1377 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1378 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1379 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1380 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1381 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1382 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1383 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1384 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1385 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1386 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1387 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1388 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1389 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1390 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1391 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1392 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1393 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1394 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1395 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1396 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1397 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1398 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1399 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1400 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1401 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1402 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1403 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1404 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1405 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1406 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1407 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1408 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1409 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1410 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1411 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1412 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1413 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1414 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1415 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1416 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1417 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1418 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1419 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1420 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1421 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1422 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1423 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1424 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1425 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1426 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1427 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1428 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1429 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1430 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1431 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1432 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1433 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1434 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1435 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1436 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1437 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1438 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1439 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1440 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1441 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1442 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1443 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1444 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1445 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1446 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1447 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1448 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1449 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1450 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1451 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 1452 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 1453 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 1454 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 1455 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 1456 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1457 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 1458 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1459 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1460 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1461 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1462 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1463 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1464 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1465 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1466 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1467 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1468 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1469 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1470 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1471 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1472 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1473 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1474 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1475 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1476 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1477 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1478 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1479 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1480 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1481 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1482 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1483 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1484 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1485 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1486 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1487 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1488 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1489 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1490 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1491 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1492 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1493 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1494 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1495 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1496 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1497 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1498 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1499 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1500 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1501 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1502 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1503 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1504 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 1505 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 1506 /* CW4010 instructions which are aliases for the cache instruction. */ 1507 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, 1508 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, 1509 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, 1510 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, 1511 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, 1512 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, 1513 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1514 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1515 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1516 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1517 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1518 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1519 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 1520 /* cfc2 is at the bottom of the table. */ 1521 /* cfc3 is at the bottom of the table. */ 1522 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1523 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 1524 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1525 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1526 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 1527 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 1528 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1529 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 1530 /* ctc2 is at the bottom of the table. */ 1531 /* ctc3 is at the bottom of the table. */ 1532 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1533 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 1534 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, 1535 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1536 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1537 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1538 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1539 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1540 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1541 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1542 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1543 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1544 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 1545 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 1546 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1547 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1548 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, 1549 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 1550 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, 1551 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1552 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, 1553 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1554 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 1555 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1556 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, 1557 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, 1558 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1559 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 1560 /* dctr and dctw are used on the r5000. */ 1561 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, 1562 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, 1563 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, 1564 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, 1565 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1566 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1567 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1568 /* For ddiv, see the comments about div. */ 1569 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1570 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, 1571 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, 1572 /* For ddivu, see the comments about div. */ 1573 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1574 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, 1575 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, 1576 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1577 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1578 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, 1579 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1580 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1581 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, 1582 /* The MIPS assembler treats the div opcode with two operands as 1583 though the first operand appeared twice (the first operand is both 1584 a source and a destination). To get the div machine instruction, 1585 you must use an explicit destination of $0. */ 1586 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1587 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1588 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, 1589 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, 1590 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1591 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1592 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 1593 /* For divu, see the comments about div. */ 1594 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1595 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 1596 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, 1597 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, 1598 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, 1599 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, 1600 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ 1601 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ 1602 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, 1603 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1604 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1605 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1606 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1607 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1608 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1609 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1610 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 1611 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, 1612 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, 1613 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1614 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 1615 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, 1616 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1617 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, 1618 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1619 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 1620 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1621 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 1622 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1623 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 1624 /* dmfc2 is at the bottom of the table. */ 1625 /* dmtc2 is at the bottom of the table. */ 1626 /* dmfc3 is at the bottom of the table. */ 1627 /* dmtc3 is at the bottom of the table. */ 1628 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, 1629 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, 1630 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, 1631 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, 1632 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, 1633 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, 1634 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1635 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1636 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ 1637 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ 1638 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1639 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, 1640 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, 1641 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 1642 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, 1643 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, 1644 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, 1645 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, 1646 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, 1647 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, 1648 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, 1649 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1650 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, 1651 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 1652 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, 1653 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, 1654 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, 1655 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, 1656 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, 1657 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, 1658 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1659 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, 1660 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1661 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1662 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ 1663 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ 1664 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1665 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1666 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1667 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ 1668 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ 1669 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1670 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 1671 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1672 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ 1673 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ 1674 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, 1675 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1676 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, 1677 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 1678 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, 1679 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, 1680 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1681 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1682 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1683 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, 1684 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1685 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, 1686 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, 1687 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1688 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1689 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 1690 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 1691 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 1692 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 1693 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 1694 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, 1695 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, 1696 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with 1697 the same hazard barrier effect. */ 1698 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, 1699 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ 1700 /* SVR4 PIC code requires special handling for j, so it must be a 1701 macro. */ 1702 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, 1703 /* This form of j is used by the disassembler and internally by the 1704 assembler, but will never match user input (because the line above 1705 will match first). */ 1706 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, 1707 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, 1708 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, 1709 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr 1710 with the same hazard barrier effect. */ 1711 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, 1712 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, 1713 /* SVR4 PIC code requires special handling for jal, so it must be a 1714 macro. */ 1715 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, 1716 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, 1717 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, 1718 /* This form of jal is used by the disassembler and internally by the 1719 assembler, but will never match user input (because the line above 1720 will match first). */ 1721 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, 1722 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, 1723 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, 1724 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1725 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, 1726 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1727 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, 1728 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, 1729 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, 1730 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, 1731 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, 1732 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1733 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 1734 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1735 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 1736 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ 1737 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, 1738 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, 1739 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1740 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, 1741 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 1742 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, 1743 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1744 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, 1745 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 1746 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, 1747 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1748 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1749 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, 1750 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1751 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, 1752 /* li is at the start of the table. */ 1753 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, 1754 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, 1755 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, 1756 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, 1757 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, 1758 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, 1759 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1760 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, 1761 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 1762 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, 1763 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1764 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, 1765 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1766 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, 1767 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1768 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 1769 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1770 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1771 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ 1772 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 1773 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1774 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, 1775 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 1776 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, 1777 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1778 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, 1779 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1780 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ 1781 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 1782 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, 1783 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 1784 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ 1785 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, 1786 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 1787 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, 1788 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 1789 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, 1790 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1791 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1792 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1793 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1794 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1795 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1796 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1797 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1798 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1799 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1800 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1801 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 1802 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1803 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 1804 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1805 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1806 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1807 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1808 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1809 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1810 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1811 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1812 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1813 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1814 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1815 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 1816 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1817 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1818 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, 1819 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1820 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1821 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1822 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1823 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1824 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1825 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 1826 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1827 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1828 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1829 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1830 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 1831 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1832 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 1833 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1834 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, 1835 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1836 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1837 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 1838 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 1839 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1840 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1841 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 1842 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 1843 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, 1844 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 1845 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1846 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 1847 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1848 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 1849 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1850 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 1851 /* mfc2 is at the bottom of the table. */ 1852 /* mfhc2 is at the bottom of the table. */ 1853 /* mfc3 is at the bottom of the table. */ 1854 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, 1855 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, 1856 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, 1857 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, 1858 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, 1859 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, 1860 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1861 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1862 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1863 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1864 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1865 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1866 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1867 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1868 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1869 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1870 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1871 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1872 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1873 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1874 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1875 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1876 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1877 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1878 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1879 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1880 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1881 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 1882 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 1883 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1884 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 1885 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 1886 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 1887 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 1888 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 1889 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 1890 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1891 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 1892 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 1893 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 1894 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1895 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1896 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1897 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1898 /* move is at the top of the table. */ 1899 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1900 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 1901 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 1902 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 1903 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1904 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1905 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1906 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 1907 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 1908 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 1909 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1910 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 1911 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, 1912 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1913 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 1914 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1915 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 1916 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1917 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 1918 /* mtc2 is at the bottom of the table. */ 1919 /* mthc2 is at the bottom of the table. */ 1920 /* mtc3 is at the bottom of the table. */ 1921 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, 1922 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, 1923 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, 1924 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, 1925 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, 1926 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, 1927 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1928 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1929 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 1930 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1931 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 1932 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1933 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1934 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1935 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, 1936 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 1937 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1938 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 1939 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 1940 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1941 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1942 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 1943 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 1944 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, 1945 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1946 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1947 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1948 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1949 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1950 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1951 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1952 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1953 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, 1954 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, 1955 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, 1956 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, 1957 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1958 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1959 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1960 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1961 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1962 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1963 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1964 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1965 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1966 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1967 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1968 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1969 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, 1970 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, 1971 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, 1972 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, 1973 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1974 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1975 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1976 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1977 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1978 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1979 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1980 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1981 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1982 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1983 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1984 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1985 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1986 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 1987 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1988 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1989 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1990 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1991 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 1992 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 1993 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 1994 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 1995 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 1996 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ 1997 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ 1998 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1999 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 2000 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 2001 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2002 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2003 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2004 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2005 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2006 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2007 /* nop is at the start of the table. */ 2008 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2009 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, 2010 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2011 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2012 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2013 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2014 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2015 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ 2016 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2017 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, 2018 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2019 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2020 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2021 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2022 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2023 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2024 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2025 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, 2026 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2027 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2028 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2029 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2030 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2031 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2032 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2033 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2034 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2035 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2036 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2037 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2038 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2039 /* pref and prefx are at the start of the table. */ 2040 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2041 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2042 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, 2043 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2044 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2045 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2046 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2047 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2048 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2049 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2050 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 2051 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2052 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2053 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2054 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2055 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2056 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2057 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2058 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2059 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2060 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2061 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2062 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, 2063 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, 2064 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2065 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, 2066 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, 2067 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, 2068 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, 2069 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, 2070 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2071 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2072 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2073 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2074 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2075 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2076 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, 2077 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, 2078 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, 2079 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, 2080 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, 2081 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, 2082 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, 2083 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, 2084 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, 2085 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, 2086 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, 2087 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2088 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2089 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2090 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2091 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2092 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2093 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2094 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2095 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2096 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2097 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2098 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2099 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2100 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2101 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2102 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, 2103 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2104 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2105 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, 2106 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, 2107 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, 2108 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, 2109 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, 2110 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2111 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, 2112 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, 2113 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, 2114 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, 2115 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, 2116 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, 2117 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, 2118 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2119 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2120 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2121 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2122 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, 2123 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, 2124 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, 2125 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, 2126 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2127 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, 2128 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, 2129 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2130 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, 2131 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2132 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, 2133 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, 2134 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2135 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2136 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2137 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2138 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, 2139 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, 2140 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, 2141 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, 2142 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, 2143 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, 2144 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, 2145 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, 2146 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, 2147 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, 2148 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2149 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, 2150 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2151 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2152 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2153 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2154 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2155 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2156 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2157 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2158 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2159 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2160 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2161 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2162 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2163 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2164 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, 2165 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, 2166 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, 2167 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, 2168 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2169 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ 2170 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2171 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2172 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2173 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2174 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2175 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2176 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, 2177 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2178 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2179 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2180 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, 2181 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, 2182 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, 2183 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, 2184 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2185 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2186 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2187 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ 2188 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2189 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2190 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2191 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ 2192 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2193 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2194 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2195 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2196 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2197 /* ssnop is at the start of the table. */ 2198 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, 2199 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2200 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, 2201 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2202 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2203 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2204 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2205 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2206 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2207 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2208 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2209 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2210 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2211 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2212 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2213 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2214 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, 2215 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, 2216 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, 2217 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2218 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, 2219 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, 2220 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, 2221 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2222 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2223 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2224 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2225 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ 2226 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2227 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, 2228 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, 2229 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, 2230 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, 2231 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2232 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, 2233 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2234 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ 2235 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2236 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, 2237 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2238 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ 2239 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, 2240 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, 2241 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, 2242 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, 2243 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, 2244 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, 2245 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, 2246 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2247 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2248 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2249 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ 2250 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, 2251 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2252 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2253 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2254 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ 2255 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, 2256 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2257 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2258 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2259 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ 2260 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, 2261 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, 2262 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, 2263 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, 2264 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, 2265 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2266 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2267 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2268 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ 2269 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, 2270 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2271 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2272 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2273 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ 2274 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, 2275 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2276 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2277 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2278 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ 2279 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, 2280 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2281 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2282 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2283 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2284 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, 2285 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2286 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2287 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, 2288 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, 2289 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, 2290 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, 2291 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, 2292 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, 2293 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, 2294 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, 2295 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, 2296 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, 2297 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, 2298 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, 2299 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, 2300 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, 2301 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, 2302 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, 2303 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, 2304 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, 2305 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2306 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, 2307 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2308 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, 2309 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, 2310 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, 2311 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, 2312 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2313 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2314 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, 2315 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2316 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2317 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2318 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2319 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2320 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2321 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, 2322 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, 2323 2324 /* User Defined Instruction. */ 2325 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2326 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2327 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2328 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2329 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2330 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2331 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2332 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2333 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2334 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2335 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2336 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2337 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2338 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2339 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2340 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2341 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2342 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2343 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2344 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2345 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2346 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2347 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2348 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2349 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2350 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2351 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2352 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2353 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2354 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2355 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2356 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2357 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2358 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2359 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2360 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2361 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2362 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2363 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2364 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2365 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2366 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2367 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2368 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2369 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2370 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2371 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2372 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2373 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2374 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2375 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2376 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2377 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2378 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2379 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2380 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2381 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2382 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2383 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2384 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2385 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2386 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2387 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2388 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 2389 2390 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format 2391 instructions so they are here for the latters to take precedence. */ 2392 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2393 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2394 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2395 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2396 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2397 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, 2398 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2399 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, 2400 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2401 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2402 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, 2403 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, 2404 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, 2405 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, 2406 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 2407 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, 2408 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, 2409 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, 2410 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, 2411 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, 2412 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, 2413 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2414 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2415 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 2416 2417 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 2418 instructions, so they are here for the latters to take precedence. */ 2419 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2420 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2421 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2422 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2423 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2424 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2425 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, 2426 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, 2427 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 2428 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, 2429 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, 2430 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, 2431 2432 /* No hazard protection on coprocessor instructions--they shouldn't 2433 change the state of the processor and if they do it's up to the 2434 user to put in nops as necessary. These are at the end so that the 2435 disassembler recognizes more specific versions first. */ 2436 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, 2437 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, 2438 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, 2439 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, 2440 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, 2441 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, 2442 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, 2443 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, 2444 /* Conflicts with the 4650's "mul" instruction. Nobody's using the 2445 4010 any more, so move this insn out of the way. If the object 2446 format gave us more info, we could do this right. */ 2447 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, 2448 /* MIPS DSP ASE */ 2449 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2450 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2451 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2452 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2453 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2454 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2455 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2456 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2457 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2458 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2459 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2460 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2461 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2462 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2463 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2464 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2465 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2466 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2467 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, 2468 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, 2469 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2470 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2471 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2472 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2473 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2474 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2475 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2476 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2477 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2478 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2479 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2480 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2481 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2482 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2483 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2484 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2485 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2486 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2487 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2488 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 2489 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 2490 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, 2491 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, 2492 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2493 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2494 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2495 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2496 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2497 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2498 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2499 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2500 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2501 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2502 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2503 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2504 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2505 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2506 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 2507 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 2508 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, 2509 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2510 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2511 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2512 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2513 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, 2514 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2515 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2516 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2517 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2518 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2519 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2520 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2521 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2522 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2523 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2524 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2525 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2526 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2527 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2528 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2529 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2530 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, 2531 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, 2532 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, 2533 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, 2534 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2535 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2536 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2537 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2538 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2539 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2540 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2541 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2542 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 2543 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 2544 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, 2545 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2546 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, 2547 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2548 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 2549 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2550 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2551 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2552 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2553 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2554 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2555 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2556 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2557 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2558 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2559 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2560 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2561 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2562 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2563 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2564 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, 2565 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2566 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2567 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2568 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2569 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2570 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2571 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2572 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2573 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 2574 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 2575 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2576 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 2577 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 2578 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2579 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2580 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2581 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2582 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2583 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2584 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2585 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2586 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2587 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2588 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2589 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2590 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2591 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2592 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2593 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2594 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2595 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2596 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2597 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2598 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2599 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2600 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2601 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2602 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2603 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2604 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2605 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2606 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2607 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2608 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2609 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2610 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2611 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2612 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2613 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2614 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2615 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2616 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2617 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2618 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, 2619 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, 2620 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, 2621 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, 2622 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, 2623 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, 2624 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, 2625 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, 2626 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, 2627 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2628 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2629 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2630 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 2631 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 2632 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, 2633 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, 2634 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2635 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2636 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2637 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2638 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2639 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2640 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2641 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2642 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2643 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2644 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2645 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2646 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2647 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2648 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2649 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2650 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2651 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2652 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2653 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2654 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2655 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 2656 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 2657 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 2658 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 2659 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2660 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2661 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2662 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2663 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2664 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2665 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2666 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, 2667 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, 2668 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2669 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2670 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2671 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2672 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2673 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2674 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2675 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2676 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2677 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2678 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2679 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 2680 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 2681 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, 2682 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, 2683 /* MIPS DSP ASE Rev2 */ 2684 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, 2685 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2686 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2687 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2688 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2689 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2690 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, 2691 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, 2692 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2693 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2694 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2695 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2696 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2697 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2698 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2699 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2700 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2701 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 2702 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2703 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2704 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2705 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2706 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 2707 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2708 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, 2709 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2710 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2711 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, 2712 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2713 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2714 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2715 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2716 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2717 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2718 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2719 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2720 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2721 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2722 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2723 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2724 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 2725 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2726 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2727 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2728 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2729 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2730 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2731 /* Move bc0* after mftr and mttr to avoid opcode collision. */ 2732 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2733 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2734 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 2735 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 2736 /* ST Microelectronics Loongson-2E and -2F. */ 2737 {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2738 {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2739 {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2740 {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2741 {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2742 {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2743 {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2744 {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2745 {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2746 {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2747 {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2748 {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2749 {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2750 {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2751 {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2752 {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2753 {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2754 {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2755 {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2756 {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2757 {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2758 {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2759 {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 2760 {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 2761 }; 2762 2763 #define MIPS_NUM_OPCODES \ 2764 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) 2765 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; 2766 2767 /* const removed from the following to allow for dynamic extensions to the 2768 * built-in instruction set. */ 2769 struct mips_opcode *mips_opcodes = 2770 (struct mips_opcode *) mips_builtin_opcodes; 2771 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; 2772 #undef MIPS_NUM_OPCODES 2773 2774 /* Mips instructions are at maximum this many bytes long. */ 2775 #define INSNLEN 4 2776 2777 2778 /* FIXME: These should be shared with gdb somehow. */ 2780 2781 struct mips_cp0sel_name 2782 { 2783 unsigned int cp0reg; 2784 unsigned int sel; 2785 const char * const name; 2786 }; 2787 2788 /* The mips16 registers. */ 2789 static const unsigned int mips16_to_32_reg_map[] = 2790 { 2791 16, 17, 2, 3, 4, 5, 6, 7 2792 }; 2793 2794 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 2795 2796 2797 static const char * const mips_gpr_names_numeric[32] = 2798 { 2799 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2800 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2801 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2802 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2803 }; 2804 2805 static const char * const mips_gpr_names_oldabi[32] = 2806 { 2807 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2808 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 2809 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2810 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2811 }; 2812 2813 static const char * const mips_gpr_names_newabi[32] = 2814 { 2815 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 2816 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 2817 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2818 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 2819 }; 2820 2821 static const char * const mips_fpr_names_numeric[32] = 2822 { 2823 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 2824 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 2825 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 2826 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 2827 }; 2828 2829 static const char * const mips_fpr_names_32[32] = 2830 { 2831 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 2832 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 2833 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 2834 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 2835 }; 2836 2837 static const char * const mips_fpr_names_n32[32] = 2838 { 2839 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 2840 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2841 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 2842 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 2843 }; 2844 2845 static const char * const mips_fpr_names_64[32] = 2846 { 2847 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 2848 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 2849 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 2850 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 2851 }; 2852 2853 static const char * const mips_cp0_names_numeric[32] = 2854 { 2855 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 2856 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 2857 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 2858 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 2859 }; 2860 2861 static const char * const mips_cp0_names_mips3264[32] = 2862 { 2863 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2864 "c0_context", "c0_pagemask", "c0_wired", "$7", 2865 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2866 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2867 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2868 "c0_xcontext", "$21", "$22", "c0_debug", 2869 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2870 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2871 }; 2872 2873 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 2874 { 2875 { 4, 1, "c0_contextconfig" }, 2876 { 0, 1, "c0_mvpcontrol" }, 2877 { 0, 2, "c0_mvpconf0" }, 2878 { 0, 3, "c0_mvpconf1" }, 2879 { 1, 1, "c0_vpecontrol" }, 2880 { 1, 2, "c0_vpeconf0" }, 2881 { 1, 3, "c0_vpeconf1" }, 2882 { 1, 4, "c0_yqmask" }, 2883 { 1, 5, "c0_vpeschedule" }, 2884 { 1, 6, "c0_vpeschefback" }, 2885 { 2, 1, "c0_tcstatus" }, 2886 { 2, 2, "c0_tcbind" }, 2887 { 2, 3, "c0_tcrestart" }, 2888 { 2, 4, "c0_tchalt" }, 2889 { 2, 5, "c0_tccontext" }, 2890 { 2, 6, "c0_tcschedule" }, 2891 { 2, 7, "c0_tcschefback" }, 2892 { 5, 1, "c0_pagegrain" }, 2893 { 6, 1, "c0_srsconf0" }, 2894 { 6, 2, "c0_srsconf1" }, 2895 { 6, 3, "c0_srsconf2" }, 2896 { 6, 4, "c0_srsconf3" }, 2897 { 6, 5, "c0_srsconf4" }, 2898 { 12, 1, "c0_intctl" }, 2899 { 12, 2, "c0_srsctl" }, 2900 { 12, 3, "c0_srsmap" }, 2901 { 15, 1, "c0_ebase" }, 2902 { 16, 1, "c0_config1" }, 2903 { 16, 2, "c0_config2" }, 2904 { 16, 3, "c0_config3" }, 2905 { 18, 1, "c0_watchlo,1" }, 2906 { 18, 2, "c0_watchlo,2" }, 2907 { 18, 3, "c0_watchlo,3" }, 2908 { 18, 4, "c0_watchlo,4" }, 2909 { 18, 5, "c0_watchlo,5" }, 2910 { 18, 6, "c0_watchlo,6" }, 2911 { 18, 7, "c0_watchlo,7" }, 2912 { 19, 1, "c0_watchhi,1" }, 2913 { 19, 2, "c0_watchhi,2" }, 2914 { 19, 3, "c0_watchhi,3" }, 2915 { 19, 4, "c0_watchhi,4" }, 2916 { 19, 5, "c0_watchhi,5" }, 2917 { 19, 6, "c0_watchhi,6" }, 2918 { 19, 7, "c0_watchhi,7" }, 2919 { 23, 1, "c0_tracecontrol" }, 2920 { 23, 2, "c0_tracecontrol2" }, 2921 { 23, 3, "c0_usertracedata" }, 2922 { 23, 4, "c0_tracebpc" }, 2923 { 25, 1, "c0_perfcnt,1" }, 2924 { 25, 2, "c0_perfcnt,2" }, 2925 { 25, 3, "c0_perfcnt,3" }, 2926 { 25, 4, "c0_perfcnt,4" }, 2927 { 25, 5, "c0_perfcnt,5" }, 2928 { 25, 6, "c0_perfcnt,6" }, 2929 { 25, 7, "c0_perfcnt,7" }, 2930 { 27, 1, "c0_cacheerr,1" }, 2931 { 27, 2, "c0_cacheerr,2" }, 2932 { 27, 3, "c0_cacheerr,3" }, 2933 { 28, 1, "c0_datalo" }, 2934 { 28, 2, "c0_taglo1" }, 2935 { 28, 3, "c0_datalo1" }, 2936 { 28, 4, "c0_taglo2" }, 2937 { 28, 5, "c0_datalo2" }, 2938 { 28, 6, "c0_taglo3" }, 2939 { 28, 7, "c0_datalo3" }, 2940 { 29, 1, "c0_datahi" }, 2941 { 29, 2, "c0_taghi1" }, 2942 { 29, 3, "c0_datahi1" }, 2943 { 29, 4, "c0_taghi2" }, 2944 { 29, 5, "c0_datahi2" }, 2945 { 29, 6, "c0_taghi3" }, 2946 { 29, 7, "c0_datahi3" }, 2947 }; 2948 2949 static const char * const mips_cp0_names_mips3264r2[32] = 2950 { 2951 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 2952 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 2953 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 2954 "c0_status", "c0_cause", "c0_epc", "c0_prid", 2955 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 2956 "c0_xcontext", "$21", "$22", "c0_debug", 2957 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 2958 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 2959 }; 2960 2961 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 2962 { 2963 { 4, 1, "c0_contextconfig" }, 2964 { 5, 1, "c0_pagegrain" }, 2965 { 12, 1, "c0_intctl" }, 2966 { 12, 2, "c0_srsctl" }, 2967 { 12, 3, "c0_srsmap" }, 2968 { 15, 1, "c0_ebase" }, 2969 { 16, 1, "c0_config1" }, 2970 { 16, 2, "c0_config2" }, 2971 { 16, 3, "c0_config3" }, 2972 { 18, 1, "c0_watchlo,1" }, 2973 { 18, 2, "c0_watchlo,2" }, 2974 { 18, 3, "c0_watchlo,3" }, 2975 { 18, 4, "c0_watchlo,4" }, 2976 { 18, 5, "c0_watchlo,5" }, 2977 { 18, 6, "c0_watchlo,6" }, 2978 { 18, 7, "c0_watchlo,7" }, 2979 { 19, 1, "c0_watchhi,1" }, 2980 { 19, 2, "c0_watchhi,2" }, 2981 { 19, 3, "c0_watchhi,3" }, 2982 { 19, 4, "c0_watchhi,4" }, 2983 { 19, 5, "c0_watchhi,5" }, 2984 { 19, 6, "c0_watchhi,6" }, 2985 { 19, 7, "c0_watchhi,7" }, 2986 { 23, 1, "c0_tracecontrol" }, 2987 { 23, 2, "c0_tracecontrol2" }, 2988 { 23, 3, "c0_usertracedata" }, 2989 { 23, 4, "c0_tracebpc" }, 2990 { 25, 1, "c0_perfcnt,1" }, 2991 { 25, 2, "c0_perfcnt,2" }, 2992 { 25, 3, "c0_perfcnt,3" }, 2993 { 25, 4, "c0_perfcnt,4" }, 2994 { 25, 5, "c0_perfcnt,5" }, 2995 { 25, 6, "c0_perfcnt,6" }, 2996 { 25, 7, "c0_perfcnt,7" }, 2997 { 27, 1, "c0_cacheerr,1" }, 2998 { 27, 2, "c0_cacheerr,2" }, 2999 { 27, 3, "c0_cacheerr,3" }, 3000 { 28, 1, "c0_datalo" }, 3001 { 28, 2, "c0_taglo1" }, 3002 { 28, 3, "c0_datalo1" }, 3003 { 28, 4, "c0_taglo2" }, 3004 { 28, 5, "c0_datalo2" }, 3005 { 28, 6, "c0_taglo3" }, 3006 { 28, 7, "c0_datalo3" }, 3007 { 29, 1, "c0_datahi" }, 3008 { 29, 2, "c0_taghi1" }, 3009 { 29, 3, "c0_datahi1" }, 3010 { 29, 4, "c0_taghi2" }, 3011 { 29, 5, "c0_datahi2" }, 3012 { 29, 6, "c0_taghi3" }, 3013 { 29, 7, "c0_datahi3" }, 3014 }; 3015 3016 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 3017 static const char * const mips_cp0_names_sb1[32] = 3018 { 3019 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 3020 "c0_context", "c0_pagemask", "c0_wired", "$7", 3021 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 3022 "c0_status", "c0_cause", "c0_epc", "c0_prid", 3023 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 3024 "c0_xcontext", "$21", "$22", "c0_debug", 3025 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 3026 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 3027 }; 3028 3029 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 3030 { 3031 { 16, 1, "c0_config1" }, 3032 { 18, 1, "c0_watchlo,1" }, 3033 { 19, 1, "c0_watchhi,1" }, 3034 { 22, 0, "c0_perftrace" }, 3035 { 23, 3, "c0_edebug" }, 3036 { 25, 1, "c0_perfcnt,1" }, 3037 { 25, 2, "c0_perfcnt,2" }, 3038 { 25, 3, "c0_perfcnt,3" }, 3039 { 25, 4, "c0_perfcnt,4" }, 3040 { 25, 5, "c0_perfcnt,5" }, 3041 { 25, 6, "c0_perfcnt,6" }, 3042 { 25, 7, "c0_perfcnt,7" }, 3043 { 26, 1, "c0_buserr_pa" }, 3044 { 27, 1, "c0_cacheerr_d" }, 3045 { 27, 3, "c0_cacheerr_d_pa" }, 3046 { 28, 1, "c0_datalo_i" }, 3047 { 28, 2, "c0_taglo_d" }, 3048 { 28, 3, "c0_datalo_d" }, 3049 { 29, 1, "c0_datahi_i" }, 3050 { 29, 2, "c0_taghi_d" }, 3051 { 29, 3, "c0_datahi_d" }, 3052 }; 3053 3054 static const char * const mips_hwr_names_numeric[32] = 3055 { 3056 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3057 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3058 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3059 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3060 }; 3061 3062 static const char * const mips_hwr_names_mips3264r2[32] = 3063 { 3064 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 3065 "$4", "$5", "$6", "$7", 3066 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3067 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3068 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3069 }; 3070 3071 struct mips_abi_choice 3072 { 3073 const char *name; 3074 const char * const *gpr_names; 3075 const char * const *fpr_names; 3076 }; 3077 3078 static struct mips_abi_choice mips_abi_choices[] = 3079 { 3080 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 3081 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 3082 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 3083 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 3084 }; 3085 3086 struct mips_arch_choice 3087 { 3088 const char *name; 3089 int bfd_mach_valid; 3090 unsigned long bfd_mach; 3091 int processor; 3092 int isa; 3093 const char * const *cp0_names; 3094 const struct mips_cp0sel_name *cp0sel_names; 3095 unsigned int cp0sel_names_len; 3096 const char * const *hwr_names; 3097 }; 3098 3099 #define bfd_mach_mips3000 3000 3100 #define bfd_mach_mips3900 3900 3101 #define bfd_mach_mips4000 4000 3102 #define bfd_mach_mips4010 4010 3103 #define bfd_mach_mips4100 4100 3104 #define bfd_mach_mips4111 4111 3105 #define bfd_mach_mips4120 4120 3106 #define bfd_mach_mips4300 4300 3107 #define bfd_mach_mips4400 4400 3108 #define bfd_mach_mips4600 4600 3109 #define bfd_mach_mips4650 4650 3110 #define bfd_mach_mips5000 5000 3111 #define bfd_mach_mips5400 5400 3112 #define bfd_mach_mips5500 5500 3113 #define bfd_mach_mips6000 6000 3114 #define bfd_mach_mips7000 7000 3115 #define bfd_mach_mips8000 8000 3116 #define bfd_mach_mips9000 9000 3117 #define bfd_mach_mips10000 10000 3118 #define bfd_mach_mips12000 12000 3119 #define bfd_mach_mips16 16 3120 #define bfd_mach_mips5 5 3121 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ 3122 #define bfd_mach_mipsisa32 32 3123 #define bfd_mach_mipsisa32r2 33 3124 #define bfd_mach_mipsisa64 64 3125 #define bfd_mach_mipsisa64r2 65 3126 3127 static const struct mips_arch_choice mips_arch_choices[] = 3128 { 3129 { "numeric", 0, 0, 0, 0, 3130 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3131 3132 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 3133 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3134 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 3135 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3136 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 3137 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3138 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 3139 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3140 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 3141 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3142 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 3143 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3144 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 3145 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3146 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 3147 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3148 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 3149 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3150 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 3151 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3152 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 3153 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3154 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 3155 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3156 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 3157 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3158 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 3159 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3160 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 3161 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3162 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3163 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3164 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3165 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3166 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 3167 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3168 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 3169 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3170 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 3171 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3172 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 3173 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3174 3175 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 3176 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 3177 _MIPS32 Architecture For Programmers Volume I: Introduction to the 3178 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 3179 page 1. */ 3180 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 3181 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, 3182 mips_cp0_names_mips3264, 3183 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3184 mips_hwr_names_numeric }, 3185 3186 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 3187 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 3188 | INSN_MIPS3D | INSN_MT), 3189 mips_cp0_names_mips3264r2, 3190 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3191 mips_hwr_names_mips3264r2 }, 3192 3193 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 3194 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 3195 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, 3196 mips_cp0_names_mips3264, 3197 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3198 mips_hwr_names_numeric }, 3199 3200 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 3201 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 3202 | INSN_DSP64 | INSN_MT | INSN_MDMX), 3203 mips_cp0_names_mips3264r2, 3204 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3205 mips_hwr_names_mips3264r2 }, 3206 3207 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 3208 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 3209 mips_cp0_names_sb1, 3210 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 3211 mips_hwr_names_numeric }, 3212 3213 /* This entry, mips16, is here only for ISA/processor selection; do 3214 not print its name. */ 3215 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 3216 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3217 }; 3218 3219 /* ISA and processor type to disassemble for, and register names to use. 3220 set_default_mips_dis_options and parse_mips_dis_options fill in these 3221 values. */ 3222 static int mips_processor; 3223 static int mips_isa; 3224 static const char * const *mips_gpr_names; 3225 static const char * const *mips_fpr_names; 3226 static const char * const *mips_cp0_names; 3227 static const struct mips_cp0sel_name *mips_cp0sel_names; 3228 static int mips_cp0sel_names_len; 3229 static const char * const *mips_hwr_names; 3230 3231 /* Other options */ 3232 static int no_aliases; /* If set disassemble as most general inst. */ 3233 3234 static const struct mips_abi_choice * 3236 choose_abi_by_name (const char *name, unsigned int namelen) 3237 { 3238 const struct mips_abi_choice *c; 3239 unsigned int i; 3240 3241 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 3242 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 3243 && strlen (mips_abi_choices[i].name) == namelen) 3244 c = &mips_abi_choices[i]; 3245 3246 return c; 3247 } 3248 3249 static const struct mips_arch_choice * 3250 choose_arch_by_name (const char *name, unsigned int namelen) 3251 { 3252 const struct mips_arch_choice *c = NULL; 3253 unsigned int i; 3254 3255 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3256 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 3257 && strlen (mips_arch_choices[i].name) == namelen) 3258 c = &mips_arch_choices[i]; 3259 3260 return c; 3261 } 3262 3263 static const struct mips_arch_choice * 3264 choose_arch_by_number (unsigned long mach) 3265 { 3266 static unsigned long hint_bfd_mach; 3267 static const struct mips_arch_choice *hint_arch_choice; 3268 const struct mips_arch_choice *c; 3269 unsigned int i; 3270 3271 /* We optimize this because even if the user specifies no 3272 flags, this will be done for every instruction! */ 3273 if (hint_bfd_mach == mach 3274 && hint_arch_choice != NULL 3275 && hint_arch_choice->bfd_mach == hint_bfd_mach) 3276 return hint_arch_choice; 3277 3278 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 3279 { 3280 if (mips_arch_choices[i].bfd_mach_valid 3281 && mips_arch_choices[i].bfd_mach == mach) 3282 { 3283 c = &mips_arch_choices[i]; 3284 hint_bfd_mach = mach; 3285 hint_arch_choice = c; 3286 } 3287 } 3288 return c; 3289 } 3290 3291 static void 3292 set_default_mips_dis_options (struct disassemble_info *info) 3293 { 3294 const struct mips_arch_choice *chosen_arch; 3295 3296 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 3297 and numeric FPR, CP0 register, and HWR names. */ 3298 mips_isa = ISA_MIPS3; 3299 mips_processor = CPU_R3000; 3300 mips_gpr_names = mips_gpr_names_oldabi; 3301 mips_fpr_names = mips_fpr_names_numeric; 3302 mips_cp0_names = mips_cp0_names_numeric; 3303 mips_cp0sel_names = NULL; 3304 mips_cp0sel_names_len = 0; 3305 mips_hwr_names = mips_hwr_names_numeric; 3306 no_aliases = 0; 3307 3308 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 3309 #if 0 3310 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 3311 { 3312 Elf_Internal_Ehdr *header; 3313 3314 header = elf_elfheader (info->section->owner); 3315 if (is_newabi (header)) 3316 mips_gpr_names = mips_gpr_names_newabi; 3317 } 3318 #endif 3319 3320 /* Set ISA, architecture, and cp0 register names as best we can. */ 3321 #if !defined(SYMTAB_AVAILABLE) && 0 3322 /* This is running out on a target machine, not in a host tool. 3323 FIXME: Where does mips_target_info come from? */ 3324 target_processor = mips_target_info.processor; 3325 mips_isa = mips_target_info.isa; 3326 #else 3327 chosen_arch = choose_arch_by_number (info->mach); 3328 if (chosen_arch != NULL) 3329 { 3330 mips_processor = chosen_arch->processor; 3331 mips_isa = chosen_arch->isa; 3332 mips_cp0_names = chosen_arch->cp0_names; 3333 mips_cp0sel_names = chosen_arch->cp0sel_names; 3334 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3335 mips_hwr_names = chosen_arch->hwr_names; 3336 } 3337 #endif 3338 } 3339 3340 static void 3341 parse_mips_dis_option (const char *option, unsigned int len) 3342 { 3343 unsigned int i, optionlen, vallen; 3344 const char *val; 3345 const struct mips_abi_choice *chosen_abi; 3346 const struct mips_arch_choice *chosen_arch; 3347 3348 /* Look for the = that delimits the end of the option name. */ 3349 for (i = 0; i < len; i++) 3350 { 3351 if (option[i] == '=') 3352 break; 3353 } 3354 if (i == 0) /* Invalid option: no name before '='. */ 3355 return; 3356 if (i == len) /* Invalid option: no '='. */ 3357 return; 3358 if (i == (len - 1)) /* Invalid option: no value after '='. */ 3359 return; 3360 3361 optionlen = i; 3362 val = option + (optionlen + 1); 3363 vallen = len - (optionlen + 1); 3364 3365 if (strncmp("gpr-names", option, optionlen) == 0 3366 && strlen("gpr-names") == optionlen) 3367 { 3368 chosen_abi = choose_abi_by_name (val, vallen); 3369 if (chosen_abi != NULL) 3370 mips_gpr_names = chosen_abi->gpr_names; 3371 return; 3372 } 3373 3374 if (strncmp("fpr-names", option, optionlen) == 0 3375 && strlen("fpr-names") == optionlen) 3376 { 3377 chosen_abi = choose_abi_by_name (val, vallen); 3378 if (chosen_abi != NULL) 3379 mips_fpr_names = chosen_abi->fpr_names; 3380 return; 3381 } 3382 3383 if (strncmp("cp0-names", option, optionlen) == 0 3384 && strlen("cp0-names") == optionlen) 3385 { 3386 chosen_arch = choose_arch_by_name (val, vallen); 3387 if (chosen_arch != NULL) 3388 { 3389 mips_cp0_names = chosen_arch->cp0_names; 3390 mips_cp0sel_names = chosen_arch->cp0sel_names; 3391 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3392 } 3393 return; 3394 } 3395 3396 if (strncmp("hwr-names", option, optionlen) == 0 3397 && strlen("hwr-names") == optionlen) 3398 { 3399 chosen_arch = choose_arch_by_name (val, vallen); 3400 if (chosen_arch != NULL) 3401 mips_hwr_names = chosen_arch->hwr_names; 3402 return; 3403 } 3404 3405 if (strncmp("reg-names", option, optionlen) == 0 3406 && strlen("reg-names") == optionlen) 3407 { 3408 /* We check both ABI and ARCH here unconditionally, so 3409 that "numeric" will do the desirable thing: select 3410 numeric register names for all registers. Other than 3411 that, a given name probably won't match both. */ 3412 chosen_abi = choose_abi_by_name (val, vallen); 3413 if (chosen_abi != NULL) 3414 { 3415 mips_gpr_names = chosen_abi->gpr_names; 3416 mips_fpr_names = chosen_abi->fpr_names; 3417 } 3418 chosen_arch = choose_arch_by_name (val, vallen); 3419 if (chosen_arch != NULL) 3420 { 3421 mips_cp0_names = chosen_arch->cp0_names; 3422 mips_cp0sel_names = chosen_arch->cp0sel_names; 3423 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 3424 mips_hwr_names = chosen_arch->hwr_names; 3425 } 3426 return; 3427 } 3428 3429 /* Invalid option. */ 3430 } 3431 3432 static void 3433 parse_mips_dis_options (const char *options) 3434 { 3435 const char *option_end; 3436 3437 if (options == NULL) 3438 return; 3439 3440 while (*options != '\0') 3441 { 3442 /* Skip empty options. */ 3443 if (*options == ',') 3444 { 3445 options++; 3446 continue; 3447 } 3448 3449 /* We know that *options is neither NUL or a comma. */ 3450 option_end = options + 1; 3451 while (*option_end != ',' && *option_end != '\0') 3452 option_end++; 3453 3454 parse_mips_dis_option (options, option_end - options); 3455 3456 /* Go on to the next one. If option_end points to a comma, it 3457 will be skipped above. */ 3458 options = option_end; 3459 } 3460 } 3461 3462 static const struct mips_cp0sel_name * 3463 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 3464 unsigned int len, 3465 unsigned int cp0reg, 3466 unsigned int sel) 3467 { 3468 unsigned int i; 3469 3470 for (i = 0; i < len; i++) 3471 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 3472 return &names[i]; 3473 return NULL; 3474 } 3475 3476 /* Print insn arguments for 32/64-bit code. */ 3478 3479 static void 3480 print_insn_args (const char *d, 3481 register unsigned long int l, 3482 bfd_vma pc, 3483 struct disassemble_info *info, 3484 const struct mips_opcode *opp) 3485 { 3486 int op, delta; 3487 unsigned int lsb, msb, msbd; 3488 3489 lsb = 0; 3490 3491 for (; *d != '\0'; d++) 3492 { 3493 switch (*d) 3494 { 3495 case ',': 3496 case '(': 3497 case ')': 3498 case '[': 3499 case ']': 3500 (*info->fprintf_func) (info->stream, "%c", *d); 3501 break; 3502 3503 case '+': 3504 /* Extension character; switch for second char. */ 3505 d++; 3506 switch (*d) 3507 { 3508 case '\0': 3509 /* xgettext:c-format */ 3510 (*info->fprintf_func) (info->stream, 3511 _("# internal error, incomplete extension sequence (+)")); 3512 return; 3513 3514 case 'A': 3515 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 3516 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3517 break; 3518 3519 case 'B': 3520 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 3521 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3522 break; 3523 3524 case '1': 3525 (*info->fprintf_func) (info->stream, "0x%lx", 3526 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 3527 break; 3528 3529 case '2': 3530 (*info->fprintf_func) (info->stream, "0x%lx", 3531 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 3532 break; 3533 3534 case '3': 3535 (*info->fprintf_func) (info->stream, "0x%lx", 3536 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 3537 break; 3538 3539 case '4': 3540 (*info->fprintf_func) (info->stream, "0x%lx", 3541 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 3542 break; 3543 3544 case 'C': 3545 case 'H': 3546 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 3547 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3548 break; 3549 3550 case 'D': 3551 { 3552 const struct mips_cp0sel_name *n; 3553 unsigned int cp0reg, sel; 3554 3555 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 3556 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3557 3558 /* CP0 register including 'sel' code for mtcN (et al.), to be 3559 printed textually if known. If not known, print both 3560 CP0 register name and sel numerically since CP0 register 3561 with sel 0 may have a name unrelated to register being 3562 printed. */ 3563 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3564 mips_cp0sel_names_len, cp0reg, sel); 3565 if (n != NULL) 3566 (*info->fprintf_func) (info->stream, "%s", n->name); 3567 else 3568 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3569 break; 3570 } 3571 3572 case 'E': 3573 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 3574 (*info->fprintf_func) (info->stream, "0x%x", lsb); 3575 break; 3576 3577 case 'F': 3578 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 3579 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 3580 break; 3581 3582 case 'G': 3583 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 3584 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 3585 break; 3586 3587 case 't': /* Coprocessor 0 reg name */ 3588 (*info->fprintf_func) (info->stream, "%s", 3589 mips_cp0_names[(l >> OP_SH_RT) & 3590 OP_MASK_RT]); 3591 break; 3592 3593 case 'T': /* Coprocessor 0 reg name */ 3594 { 3595 const struct mips_cp0sel_name *n; 3596 unsigned int cp0reg, sel; 3597 3598 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 3599 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 3600 3601 /* CP0 register including 'sel' code for mftc0, to be 3602 printed textually if known. If not known, print both 3603 CP0 register name and sel numerically since CP0 register 3604 with sel 0 may have a name unrelated to register being 3605 printed. */ 3606 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 3607 mips_cp0sel_names_len, cp0reg, sel); 3608 if (n != NULL) 3609 (*info->fprintf_func) (info->stream, "%s", n->name); 3610 else 3611 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 3612 break; 3613 } 3614 3615 default: 3616 /* xgettext:c-format */ 3617 (*info->fprintf_func) (info->stream, 3618 _("# internal error, undefined extension sequence (+%c)"), 3619 *d); 3620 return; 3621 } 3622 break; 3623 3624 case '2': 3625 (*info->fprintf_func) (info->stream, "0x%lx", 3626 (l >> OP_SH_BP) & OP_MASK_BP); 3627 break; 3628 3629 case '3': 3630 (*info->fprintf_func) (info->stream, "0x%lx", 3631 (l >> OP_SH_SA3) & OP_MASK_SA3); 3632 break; 3633 3634 case '4': 3635 (*info->fprintf_func) (info->stream, "0x%lx", 3636 (l >> OP_SH_SA4) & OP_MASK_SA4); 3637 break; 3638 3639 case '5': 3640 (*info->fprintf_func) (info->stream, "0x%lx", 3641 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 3642 break; 3643 3644 case '6': 3645 (*info->fprintf_func) (info->stream, "0x%lx", 3646 (l >> OP_SH_RS) & OP_MASK_RS); 3647 break; 3648 3649 case '7': 3650 (*info->fprintf_func) (info->stream, "$ac%ld", 3651 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 3652 break; 3653 3654 case '8': 3655 (*info->fprintf_func) (info->stream, "0x%lx", 3656 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 3657 break; 3658 3659 case '9': 3660 (*info->fprintf_func) (info->stream, "$ac%ld", 3661 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 3662 break; 3663 3664 case '0': /* dsp 6-bit signed immediate in bit 20 */ 3665 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 3666 if (delta & 0x20) /* test sign bit */ 3667 delta |= ~OP_MASK_DSPSFT; 3668 (*info->fprintf_func) (info->stream, "%d", delta); 3669 break; 3670 3671 case ':': /* dsp 7-bit signed immediate in bit 19 */ 3672 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 3673 if (delta & 0x40) /* test sign bit */ 3674 delta |= ~OP_MASK_DSPSFT_7; 3675 (*info->fprintf_func) (info->stream, "%d", delta); 3676 break; 3677 3678 case '\'': 3679 (*info->fprintf_func) (info->stream, "0x%lx", 3680 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 3681 break; 3682 3683 case '@': /* dsp 10-bit signed immediate in bit 16 */ 3684 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 3685 if (delta & 0x200) /* test sign bit */ 3686 delta |= ~OP_MASK_IMM10; 3687 (*info->fprintf_func) (info->stream, "%d", delta); 3688 break; 3689 3690 case '!': 3691 (*info->fprintf_func) (info->stream, "%ld", 3692 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 3693 break; 3694 3695 case '$': 3696 (*info->fprintf_func) (info->stream, "%ld", 3697 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 3698 break; 3699 3700 case '*': 3701 (*info->fprintf_func) (info->stream, "$ac%ld", 3702 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 3703 break; 3704 3705 case '&': 3706 (*info->fprintf_func) (info->stream, "$ac%ld", 3707 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 3708 break; 3709 3710 case 'g': 3711 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 3712 (*info->fprintf_func) (info->stream, "$%ld", 3713 (l >> OP_SH_RD) & OP_MASK_RD); 3714 break; 3715 3716 case 's': 3717 case 'b': 3718 case 'r': 3719 case 'v': 3720 (*info->fprintf_func) (info->stream, "%s", 3721 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 3722 break; 3723 3724 case 't': 3725 case 'w': 3726 (*info->fprintf_func) (info->stream, "%s", 3727 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3728 break; 3729 3730 case 'i': 3731 case 'u': 3732 (*info->fprintf_func) (info->stream, "0x%lx", 3733 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 3734 break; 3735 3736 case 'j': /* Same as i, but sign-extended. */ 3737 case 'o': 3738 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3739 if (delta & 0x8000) 3740 delta |= ~0xffff; 3741 (*info->fprintf_func) (info->stream, "%d", 3742 delta); 3743 break; 3744 3745 case 'h': 3746 (*info->fprintf_func) (info->stream, "0x%x", 3747 (unsigned int) ((l >> OP_SH_PREFX) 3748 & OP_MASK_PREFX)); 3749 break; 3750 3751 case 'k': 3752 (*info->fprintf_func) (info->stream, "0x%x", 3753 (unsigned int) ((l >> OP_SH_CACHE) 3754 & OP_MASK_CACHE)); 3755 break; 3756 3757 case 'a': 3758 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 3759 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 3760 /* For gdb disassembler, force odd address on jalx. */ 3761 if (info->flavour == bfd_target_unknown_flavour 3762 && strcmp (opp->name, "jalx") == 0) 3763 info->target |= 1; 3764 (*info->print_address_func) (info->target, info); 3765 break; 3766 3767 case 'p': 3768 /* Sign extend the displacement. */ 3769 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 3770 if (delta & 0x8000) 3771 delta |= ~0xffff; 3772 info->target = (delta << 2) + pc + INSNLEN; 3773 (*info->print_address_func) (info->target, info); 3774 break; 3775 3776 case 'd': 3777 (*info->fprintf_func) (info->stream, "%s", 3778 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3779 break; 3780 3781 case 'U': 3782 { 3783 /* First check for both rd and rt being equal. */ 3784 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 3785 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 3786 (*info->fprintf_func) (info->stream, "%s", 3787 mips_gpr_names[reg]); 3788 else 3789 { 3790 /* If one is zero use the other. */ 3791 if (reg == 0) 3792 (*info->fprintf_func) (info->stream, "%s", 3793 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3794 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 3795 (*info->fprintf_func) (info->stream, "%s", 3796 mips_gpr_names[reg]); 3797 else /* Bogus, result depends on processor. */ 3798 (*info->fprintf_func) (info->stream, "%s or %s", 3799 mips_gpr_names[reg], 3800 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 3801 } 3802 } 3803 break; 3804 3805 case 'z': 3806 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 3807 break; 3808 3809 case '<': 3810 (*info->fprintf_func) (info->stream, "0x%lx", 3811 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 3812 break; 3813 3814 case 'c': 3815 (*info->fprintf_func) (info->stream, "0x%lx", 3816 (l >> OP_SH_CODE) & OP_MASK_CODE); 3817 break; 3818 3819 case 'q': 3820 (*info->fprintf_func) (info->stream, "0x%lx", 3821 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 3822 break; 3823 3824 case 'C': 3825 (*info->fprintf_func) (info->stream, "0x%lx", 3826 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 3827 break; 3828 3829 case 'B': 3830 (*info->fprintf_func) (info->stream, "0x%lx", 3831 3832 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 3833 break; 3834 3835 case 'J': 3836 (*info->fprintf_func) (info->stream, "0x%lx", 3837 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 3838 break; 3839 3840 case 'S': 3841 case 'V': 3842 (*info->fprintf_func) (info->stream, "%s", 3843 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 3844 break; 3845 3846 case 'T': 3847 case 'W': 3848 (*info->fprintf_func) (info->stream, "%s", 3849 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 3850 break; 3851 3852 case 'D': 3853 (*info->fprintf_func) (info->stream, "%s", 3854 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 3855 break; 3856 3857 case 'R': 3858 (*info->fprintf_func) (info->stream, "%s", 3859 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 3860 break; 3861 3862 case 'E': 3863 /* Coprocessor register for lwcN instructions, et al. 3864 3865 Note that there is no load/store cp0 instructions, and 3866 that FPU (cp1) instructions disassemble this field using 3867 'T' format. Therefore, until we gain understanding of 3868 cp2 register names, we can simply print the register 3869 numbers. */ 3870 (*info->fprintf_func) (info->stream, "$%ld", 3871 (l >> OP_SH_RT) & OP_MASK_RT); 3872 break; 3873 3874 case 'G': 3875 /* Coprocessor register for mtcN instructions, et al. Note 3876 that FPU (cp1) instructions disassemble this field using 3877 'S' format. Therefore, we only need to worry about cp0, 3878 cp2, and cp3. */ 3879 op = (l >> OP_SH_OP) & OP_MASK_OP; 3880 if (op == OP_OP_COP0) 3881 (*info->fprintf_func) (info->stream, "%s", 3882 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3883 else 3884 (*info->fprintf_func) (info->stream, "$%ld", 3885 (l >> OP_SH_RD) & OP_MASK_RD); 3886 break; 3887 3888 case 'K': 3889 (*info->fprintf_func) (info->stream, "%s", 3890 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 3891 break; 3892 3893 case 'N': 3894 (*info->fprintf_func) (info->stream, 3895 ((opp->pinfo & (FP_D | FP_S)) != 0 3896 ? "$fcc%ld" : "$cc%ld"), 3897 (l >> OP_SH_BCC) & OP_MASK_BCC); 3898 break; 3899 3900 case 'M': 3901 (*info->fprintf_func) (info->stream, "$fcc%ld", 3902 (l >> OP_SH_CCC) & OP_MASK_CCC); 3903 break; 3904 3905 case 'P': 3906 (*info->fprintf_func) (info->stream, "%ld", 3907 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 3908 break; 3909 3910 case 'e': 3911 (*info->fprintf_func) (info->stream, "%ld", 3912 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 3913 break; 3914 3915 case '%': 3916 (*info->fprintf_func) (info->stream, "%ld", 3917 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 3918 break; 3919 3920 case 'H': 3921 (*info->fprintf_func) (info->stream, "%ld", 3922 (l >> OP_SH_SEL) & OP_MASK_SEL); 3923 break; 3924 3925 case 'O': 3926 (*info->fprintf_func) (info->stream, "%ld", 3927 (l >> OP_SH_ALN) & OP_MASK_ALN); 3928 break; 3929 3930 case 'Q': 3931 { 3932 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 3933 3934 if ((vsel & 0x10) == 0) 3935 { 3936 int fmt; 3937 3938 vsel &= 0x0f; 3939 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 3940 if ((vsel & 1) == 0) 3941 break; 3942 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 3943 (l >> OP_SH_FT) & OP_MASK_FT, 3944 vsel >> 1); 3945 } 3946 else if ((vsel & 0x08) == 0) 3947 { 3948 (*info->fprintf_func) (info->stream, "$v%ld", 3949 (l >> OP_SH_FT) & OP_MASK_FT); 3950 } 3951 else 3952 { 3953 (*info->fprintf_func) (info->stream, "0x%lx", 3954 (l >> OP_SH_FT) & OP_MASK_FT); 3955 } 3956 } 3957 break; 3958 3959 case 'X': 3960 (*info->fprintf_func) (info->stream, "$v%ld", 3961 (l >> OP_SH_FD) & OP_MASK_FD); 3962 break; 3963 3964 case 'Y': 3965 (*info->fprintf_func) (info->stream, "$v%ld", 3966 (l >> OP_SH_FS) & OP_MASK_FS); 3967 break; 3968 3969 case 'Z': 3970 (*info->fprintf_func) (info->stream, "$v%ld", 3971 (l >> OP_SH_FT) & OP_MASK_FT); 3972 break; 3973 3974 default: 3975 /* xgettext:c-format */ 3976 (*info->fprintf_func) (info->stream, 3977 _("# internal error, undefined modifier(%c)"), 3978 *d); 3979 return; 3980 } 3981 } 3982 } 3983 3984 /* Check if the object uses NewABI conventions. */ 3986 #if 0 3987 static int 3988 is_newabi (header) 3989 Elf_Internal_Ehdr *header; 3990 { 3991 /* There are no old-style ABIs which use 64-bit ELF. */ 3992 if (header->e_ident[EI_CLASS] == ELFCLASS64) 3993 return 1; 3994 3995 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 3996 if ((header->e_flags & EF_MIPS_ABI2) != 0) 3997 return 1; 3998 3999 return 0; 4000 } 4001 #endif 4002 4003 /* Print the mips instruction at address MEMADDR in debugged memory, 4005 on using INFO. Returns length of the instruction, in bytes, which is 4006 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 4007 this is little-endian code. */ 4008 4009 static int 4010 print_insn_mips (bfd_vma memaddr, 4011 unsigned long int word, 4012 struct disassemble_info *info) 4013 { 4014 const struct mips_opcode *op; 4015 static bfd_boolean init = 0; 4016 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 4017 4018 /* Build a hash table to shorten the search time. */ 4019 if (! init) 4020 { 4021 unsigned int i; 4022 4023 for (i = 0; i <= OP_MASK_OP; i++) 4024 { 4025 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 4026 { 4027 if (op->pinfo == INSN_MACRO 4028 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 4029 continue; 4030 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 4031 { 4032 mips_hash[i] = op; 4033 break; 4034 } 4035 } 4036 } 4037 4038 init = 1; 4039 } 4040 4041 info->bytes_per_chunk = INSNLEN; 4042 info->display_endian = info->endian; 4043 info->insn_info_valid = 1; 4044 info->branch_delay_insns = 0; 4045 info->data_size = 0; 4046 info->insn_type = dis_nonbranch; 4047 info->target = 0; 4048 info->target2 = 0; 4049 4050 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 4051 if (op != NULL) 4052 { 4053 for (; op < &mips_opcodes[NUMOPCODES]; op++) 4054 { 4055 if (op->pinfo != INSN_MACRO 4056 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4057 && (word & op->mask) == op->match) 4058 { 4059 const char *d; 4060 4061 /* We always allow to disassemble the jalx instruction. */ 4062 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 4063 && strcmp (op->name, "jalx")) 4064 continue; 4065 4066 /* Figure out instruction type and branch delay information. */ 4067 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4068 { 4069 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4070 info->insn_type = dis_jsr; 4071 else 4072 info->insn_type = dis_branch; 4073 info->branch_delay_insns = 1; 4074 } 4075 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 4076 | INSN_COND_BRANCH_LIKELY)) != 0) 4077 { 4078 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4079 info->insn_type = dis_condjsr; 4080 else 4081 info->insn_type = dis_condbranch; 4082 info->branch_delay_insns = 1; 4083 } 4084 else if ((op->pinfo & (INSN_STORE_MEMORY 4085 | INSN_LOAD_MEMORY_DELAY)) != 0) 4086 info->insn_type = dis_dref; 4087 4088 (*info->fprintf_func) (info->stream, "%s", op->name); 4089 4090 d = op->args; 4091 if (d != NULL && *d != '\0') 4092 { 4093 (*info->fprintf_func) (info->stream, "\t"); 4094 print_insn_args (d, word, memaddr, info, op); 4095 } 4096 4097 return INSNLEN; 4098 } 4099 } 4100 } 4101 4102 /* Handle undefined instructions. */ 4103 info->insn_type = dis_noninsn; 4104 (*info->fprintf_func) (info->stream, "0x%lx", word); 4105 return INSNLEN; 4106 } 4107 4108 /* In an environment where we do not know the symbol type of the 4110 instruction we are forced to assume that the low order bit of the 4111 instructions' address may mark it as a mips16 instruction. If we 4112 are single stepping, or the pc is within the disassembled function, 4113 this works. Otherwise, we need a clue. Sometimes. */ 4114 4115 static int 4116 _print_insn_mips (bfd_vma memaddr, 4117 struct disassemble_info *info, 4118 enum bfd_endian endianness) 4119 { 4120 bfd_byte buffer[INSNLEN]; 4121 int status; 4122 4123 set_default_mips_dis_options (info); 4124 parse_mips_dis_options (info->disassembler_options); 4125 4126 #if 0 4127 #if 1 4128 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 4129 /* Only a few tools will work this way. */ 4130 if (memaddr & 0x01) 4131 return print_insn_mips16 (memaddr, info); 4132 #endif 4133 4134 #if SYMTAB_AVAILABLE 4135 if (info->mach == bfd_mach_mips16 4136 || (info->flavour == bfd_target_elf_flavour 4137 && info->symbols != NULL 4138 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other 4139 == STO_MIPS16))) 4140 return print_insn_mips16 (memaddr, info); 4141 #endif 4142 #endif 4143 4144 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 4145 if (status == 0) 4146 { 4147 unsigned long insn; 4148 4149 if (endianness == BFD_ENDIAN_BIG) 4150 insn = (unsigned long) bfd_getb32 (buffer); 4151 else 4152 insn = (unsigned long) bfd_getl32 (buffer); 4153 4154 return print_insn_mips (memaddr, insn, info); 4155 } 4156 else 4157 { 4158 (*info->memory_error_func) (status, memaddr, info); 4159 return -1; 4160 } 4161 } 4162 4163 int 4164 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 4165 { 4166 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 4167 } 4168 4169 int 4170 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 4171 { 4172 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 4173 } 4174 4175 /* Disassemble mips16 instructions. */ 4177 #if 0 4178 static int 4179 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 4180 { 4181 int status; 4182 bfd_byte buffer[2]; 4183 int length; 4184 int insn; 4185 bfd_boolean use_extend; 4186 int extend = 0; 4187 const struct mips_opcode *op, *opend; 4188 4189 info->bytes_per_chunk = 2; 4190 info->display_endian = info->endian; 4191 info->insn_info_valid = 1; 4192 info->branch_delay_insns = 0; 4193 info->data_size = 0; 4194 info->insn_type = dis_nonbranch; 4195 info->target = 0; 4196 info->target2 = 0; 4197 4198 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4199 if (status != 0) 4200 { 4201 (*info->memory_error_func) (status, memaddr, info); 4202 return -1; 4203 } 4204 4205 length = 2; 4206 4207 if (info->endian == BFD_ENDIAN_BIG) 4208 insn = bfd_getb16 (buffer); 4209 else 4210 insn = bfd_getl16 (buffer); 4211 4212 /* Handle the extend opcode specially. */ 4213 use_extend = FALSE; 4214 if ((insn & 0xf800) == 0xf000) 4215 { 4216 use_extend = TRUE; 4217 extend = insn & 0x7ff; 4218 4219 memaddr += 2; 4220 4221 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 4222 if (status != 0) 4223 { 4224 (*info->fprintf_func) (info->stream, "extend 0x%x", 4225 (unsigned int) extend); 4226 (*info->memory_error_func) (status, memaddr, info); 4227 return -1; 4228 } 4229 4230 if (info->endian == BFD_ENDIAN_BIG) 4231 insn = bfd_getb16 (buffer); 4232 else 4233 insn = bfd_getl16 (buffer); 4234 4235 /* Check for an extend opcode followed by an extend opcode. */ 4236 if ((insn & 0xf800) == 0xf000) 4237 { 4238 (*info->fprintf_func) (info->stream, "extend 0x%x", 4239 (unsigned int) extend); 4240 info->insn_type = dis_noninsn; 4241 return length; 4242 } 4243 4244 length += 2; 4245 } 4246 4247 /* FIXME: Should probably use a hash table on the major opcode here. */ 4248 4249 opend = mips16_opcodes + bfd_mips16_num_opcodes; 4250 for (op = mips16_opcodes; op < opend; op++) 4251 { 4252 if (op->pinfo != INSN_MACRO 4253 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4254 && (insn & op->mask) == op->match) 4255 { 4256 const char *s; 4257 4258 if (strchr (op->args, 'a') != NULL) 4259 { 4260 if (use_extend) 4261 { 4262 (*info->fprintf_func) (info->stream, "extend 0x%x", 4263 (unsigned int) extend); 4264 info->insn_type = dis_noninsn; 4265 return length - 2; 4266 } 4267 4268 use_extend = FALSE; 4269 4270 memaddr += 2; 4271 4272 status = (*info->read_memory_func) (memaddr, buffer, 2, 4273 info); 4274 if (status == 0) 4275 { 4276 use_extend = TRUE; 4277 if (info->endian == BFD_ENDIAN_BIG) 4278 extend = bfd_getb16 (buffer); 4279 else 4280 extend = bfd_getl16 (buffer); 4281 length += 2; 4282 } 4283 } 4284 4285 (*info->fprintf_func) (info->stream, "%s", op->name); 4286 if (op->args[0] != '\0') 4287 (*info->fprintf_func) (info->stream, "\t"); 4288 4289 for (s = op->args; *s != '\0'; s++) 4290 { 4291 if (*s == ',' 4292 && s[1] == 'w' 4293 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 4294 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 4295 { 4296 /* Skip the register and the comma. */ 4297 ++s; 4298 continue; 4299 } 4300 if (*s == ',' 4301 && s[1] == 'v' 4302 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 4303 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 4304 { 4305 /* Skip the register and the comma. */ 4306 ++s; 4307 continue; 4308 } 4309 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 4310 info); 4311 } 4312 4313 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4314 { 4315 info->branch_delay_insns = 1; 4316 if (info->insn_type != dis_jsr) 4317 info->insn_type = dis_branch; 4318 } 4319 4320 return length; 4321 } 4322 } 4323 4324 if (use_extend) 4325 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 4326 (*info->fprintf_func) (info->stream, "0x%x", insn); 4327 info->insn_type = dis_noninsn; 4328 4329 return length; 4330 } 4331 4332 /* Disassemble an operand for a mips16 instruction. */ 4333 4334 static void 4335 print_mips16_insn_arg (char type, 4336 const struct mips_opcode *op, 4337 int l, 4338 bfd_boolean use_extend, 4339 int extend, 4340 bfd_vma memaddr, 4341 struct disassemble_info *info) 4342 { 4343 switch (type) 4344 { 4345 case ',': 4346 case '(': 4347 case ')': 4348 (*info->fprintf_func) (info->stream, "%c", type); 4349 break; 4350 4351 case 'y': 4352 case 'w': 4353 (*info->fprintf_func) (info->stream, "%s", 4354 mips16_reg_names(((l >> MIPS16OP_SH_RY) 4355 & MIPS16OP_MASK_RY))); 4356 break; 4357 4358 case 'x': 4359 case 'v': 4360 (*info->fprintf_func) (info->stream, "%s", 4361 mips16_reg_names(((l >> MIPS16OP_SH_RX) 4362 & MIPS16OP_MASK_RX))); 4363 break; 4364 4365 case 'z': 4366 (*info->fprintf_func) (info->stream, "%s", 4367 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 4368 & MIPS16OP_MASK_RZ))); 4369 break; 4370 4371 case 'Z': 4372 (*info->fprintf_func) (info->stream, "%s", 4373 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 4374 & MIPS16OP_MASK_MOVE32Z))); 4375 break; 4376 4377 case '0': 4378 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 4379 break; 4380 4381 case 'S': 4382 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 4383 break; 4384 4385 case 'P': 4386 (*info->fprintf_func) (info->stream, "$pc"); 4387 break; 4388 4389 case 'R': 4390 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 4391 break; 4392 4393 case 'X': 4394 (*info->fprintf_func) (info->stream, "%s", 4395 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 4396 & MIPS16OP_MASK_REGR32)]); 4397 break; 4398 4399 case 'Y': 4400 (*info->fprintf_func) (info->stream, "%s", 4401 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 4402 break; 4403 4404 case '<': 4405 case '>': 4406 case '[': 4407 case ']': 4408 case '4': 4409 case '5': 4410 case 'H': 4411 case 'W': 4412 case 'D': 4413 case 'j': 4414 case '6': 4415 case '8': 4416 case 'V': 4417 case 'C': 4418 case 'U': 4419 case 'k': 4420 case 'K': 4421 case 'p': 4422 case 'q': 4423 case 'A': 4424 case 'B': 4425 case 'E': 4426 { 4427 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 4428 4429 shift = 0; 4430 signedp = 0; 4431 extbits = 16; 4432 pcrel = 0; 4433 extu = 0; 4434 branch = 0; 4435 switch (type) 4436 { 4437 case '<': 4438 nbits = 3; 4439 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4440 extbits = 5; 4441 extu = 1; 4442 break; 4443 case '>': 4444 nbits = 3; 4445 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4446 extbits = 5; 4447 extu = 1; 4448 break; 4449 case '[': 4450 nbits = 3; 4451 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 4452 extbits = 6; 4453 extu = 1; 4454 break; 4455 case ']': 4456 nbits = 3; 4457 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 4458 extbits = 6; 4459 extu = 1; 4460 break; 4461 case '4': 4462 nbits = 4; 4463 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 4464 signedp = 1; 4465 extbits = 15; 4466 break; 4467 case '5': 4468 nbits = 5; 4469 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4470 info->insn_type = dis_dref; 4471 info->data_size = 1; 4472 break; 4473 case 'H': 4474 nbits = 5; 4475 shift = 1; 4476 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4477 info->insn_type = dis_dref; 4478 info->data_size = 2; 4479 break; 4480 case 'W': 4481 nbits = 5; 4482 shift = 2; 4483 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4484 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 4485 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 4486 { 4487 info->insn_type = dis_dref; 4488 info->data_size = 4; 4489 } 4490 break; 4491 case 'D': 4492 nbits = 5; 4493 shift = 3; 4494 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4495 info->insn_type = dis_dref; 4496 info->data_size = 8; 4497 break; 4498 case 'j': 4499 nbits = 5; 4500 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4501 signedp = 1; 4502 break; 4503 case '6': 4504 nbits = 6; 4505 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4506 break; 4507 case '8': 4508 nbits = 8; 4509 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4510 break; 4511 case 'V': 4512 nbits = 8; 4513 shift = 2; 4514 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4515 /* FIXME: This might be lw, or it might be addiu to $sp or 4516 $pc. We assume it's load. */ 4517 info->insn_type = dis_dref; 4518 info->data_size = 4; 4519 break; 4520 case 'C': 4521 nbits = 8; 4522 shift = 3; 4523 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4524 info->insn_type = dis_dref; 4525 info->data_size = 8; 4526 break; 4527 case 'U': 4528 nbits = 8; 4529 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4530 extu = 1; 4531 break; 4532 case 'k': 4533 nbits = 8; 4534 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4535 signedp = 1; 4536 break; 4537 case 'K': 4538 nbits = 8; 4539 shift = 3; 4540 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4541 signedp = 1; 4542 break; 4543 case 'p': 4544 nbits = 8; 4545 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4546 signedp = 1; 4547 pcrel = 1; 4548 branch = 1; 4549 info->insn_type = dis_condbranch; 4550 break; 4551 case 'q': 4552 nbits = 11; 4553 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 4554 signedp = 1; 4555 pcrel = 1; 4556 branch = 1; 4557 info->insn_type = dis_branch; 4558 break; 4559 case 'A': 4560 nbits = 8; 4561 shift = 2; 4562 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 4563 pcrel = 1; 4564 /* FIXME: This can be lw or la. We assume it is lw. */ 4565 info->insn_type = dis_dref; 4566 info->data_size = 4; 4567 break; 4568 case 'B': 4569 nbits = 5; 4570 shift = 3; 4571 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4572 pcrel = 1; 4573 info->insn_type = dis_dref; 4574 info->data_size = 8; 4575 break; 4576 case 'E': 4577 nbits = 5; 4578 shift = 2; 4579 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 4580 pcrel = 1; 4581 break; 4582 default: 4583 abort (); 4584 } 4585 4586 if (! use_extend) 4587 { 4588 if (signedp && immed >= (1 << (nbits - 1))) 4589 immed -= 1 << nbits; 4590 immed <<= shift; 4591 if ((type == '<' || type == '>' || type == '[' || type == ']') 4592 && immed == 0) 4593 immed = 8; 4594 } 4595 else 4596 { 4597 if (extbits == 16) 4598 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 4599 else if (extbits == 15) 4600 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 4601 else 4602 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 4603 immed &= (1 << extbits) - 1; 4604 if (! extu && immed >= (1 << (extbits - 1))) 4605 immed -= 1 << extbits; 4606 } 4607 4608 if (! pcrel) 4609 (*info->fprintf_func) (info->stream, "%d", immed); 4610 else 4611 { 4612 bfd_vma baseaddr; 4613 4614 if (branch) 4615 { 4616 immed *= 2; 4617 baseaddr = memaddr + 2; 4618 } 4619 else if (use_extend) 4620 baseaddr = memaddr - 2; 4621 else 4622 { 4623 int status; 4624 bfd_byte buffer[2]; 4625 4626 baseaddr = memaddr; 4627 4628 /* If this instruction is in the delay slot of a jr 4629 instruction, the base address is the address of the 4630 jr instruction. If it is in the delay slot of jalr 4631 instruction, the base address is the address of the 4632 jalr instruction. This test is unreliable: we have 4633 no way of knowing whether the previous word is 4634 instruction or data. */ 4635 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 4636 info); 4637 if (status == 0 4638 && (((info->endian == BFD_ENDIAN_BIG 4639 ? bfd_getb16 (buffer) 4640 : bfd_getl16 (buffer)) 4641 & 0xf800) == 0x1800)) 4642 baseaddr = memaddr - 4; 4643 else 4644 { 4645 status = (*info->read_memory_func) (memaddr - 2, buffer, 4646 2, info); 4647 if (status == 0 4648 && (((info->endian == BFD_ENDIAN_BIG 4649 ? bfd_getb16 (buffer) 4650 : bfd_getl16 (buffer)) 4651 & 0xf81f) == 0xe800)) 4652 baseaddr = memaddr - 2; 4653 } 4654 } 4655 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 4656 if (pcrel && branch 4657 && info->flavour == bfd_target_unknown_flavour) 4658 /* For gdb disassembler, maintain odd address. */ 4659 info->target |= 1; 4660 (*info->print_address_func) (info->target, info); 4661 } 4662 } 4663 break; 4664 4665 case 'a': 4666 { 4667 int jalx = l & 0x400; 4668 4669 if (! use_extend) 4670 extend = 0; 4671 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 4672 if (!jalx && info->flavour == bfd_target_unknown_flavour) 4673 /* For gdb disassembler, maintain odd address. */ 4674 l |= 1; 4675 } 4676 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 4677 (*info->print_address_func) (info->target, info); 4678 info->insn_type = dis_jsr; 4679 info->branch_delay_insns = 1; 4680 break; 4681 4682 case 'l': 4683 case 'L': 4684 { 4685 int need_comma, amask, smask; 4686 4687 need_comma = 0; 4688 4689 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 4690 4691 amask = (l >> 3) & 7; 4692 4693 if (amask > 0 && amask < 5) 4694 { 4695 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4696 if (amask > 1) 4697 (*info->fprintf_func) (info->stream, "-%s", 4698 mips_gpr_names[amask + 3]); 4699 need_comma = 1; 4700 } 4701 4702 smask = (l >> 1) & 3; 4703 if (smask == 3) 4704 { 4705 (*info->fprintf_func) (info->stream, "%s??", 4706 need_comma ? "," : ""); 4707 need_comma = 1; 4708 } 4709 else if (smask > 0) 4710 { 4711 (*info->fprintf_func) (info->stream, "%s%s", 4712 need_comma ? "," : "", 4713 mips_gpr_names[16]); 4714 if (smask > 1) 4715 (*info->fprintf_func) (info->stream, "-%s", 4716 mips_gpr_names[smask + 15]); 4717 need_comma = 1; 4718 } 4719 4720 if (l & 1) 4721 { 4722 (*info->fprintf_func) (info->stream, "%s%s", 4723 need_comma ? "," : "", 4724 mips_gpr_names[31]); 4725 need_comma = 1; 4726 } 4727 4728 if (amask == 5 || amask == 6) 4729 { 4730 (*info->fprintf_func) (info->stream, "%s$f0", 4731 need_comma ? "," : ""); 4732 if (amask == 6) 4733 (*info->fprintf_func) (info->stream, "-$f1"); 4734 } 4735 } 4736 break; 4737 4738 case 'm': 4739 case 'M': 4740 /* MIPS16e save/restore. */ 4741 { 4742 int need_comma = 0; 4743 int amask, args, statics; 4744 int nsreg, smask; 4745 int framesz; 4746 int i, j; 4747 4748 l = l & 0x7f; 4749 if (use_extend) 4750 l |= extend << 16; 4751 4752 amask = (l >> 16) & 0xf; 4753 if (amask == MIPS16_ALL_ARGS) 4754 { 4755 args = 4; 4756 statics = 0; 4757 } 4758 else if (amask == MIPS16_ALL_STATICS) 4759 { 4760 args = 0; 4761 statics = 4; 4762 } 4763 else 4764 { 4765 args = amask >> 2; 4766 statics = amask & 3; 4767 } 4768 4769 if (args > 0) { 4770 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 4771 if (args > 1) 4772 (*info->fprintf_func) (info->stream, "-%s", 4773 mips_gpr_names[4 + args - 1]); 4774 need_comma = 1; 4775 } 4776 4777 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 4778 if (framesz == 0 && !use_extend) 4779 framesz = 128; 4780 4781 (*info->fprintf_func) (info->stream, "%s%d", 4782 need_comma ? "," : "", 4783 framesz); 4784 4785 if (l & 0x40) /* $ra */ 4786 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 4787 4788 nsreg = (l >> 24) & 0x7; 4789 smask = 0; 4790 if (l & 0x20) /* $s0 */ 4791 smask |= 1 << 0; 4792 if (l & 0x10) /* $s1 */ 4793 smask |= 1 << 1; 4794 if (nsreg > 0) /* $s2-$s8 */ 4795 smask |= ((1 << nsreg) - 1) << 2; 4796 4797 /* Find first set static reg bit. */ 4798 for (i = 0; i < 9; i++) 4799 { 4800 if (smask & (1 << i)) 4801 { 4802 (*info->fprintf_func) (info->stream, ",%s", 4803 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 4804 /* Skip over string of set bits. */ 4805 for (j = i; smask & (2 << j); j++) 4806 continue; 4807 if (j > i) 4808 (*info->fprintf_func) (info->stream, "-%s", 4809 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 4810 i = j + 1; 4811 } 4812 } 4813 4814 /* Statics $ax - $a3. */ 4815 if (statics == 1) 4816 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 4817 else if (statics > 0) 4818 (*info->fprintf_func) (info->stream, ",%s-%s", 4819 mips_gpr_names[7 - statics + 1], 4820 mips_gpr_names[7]); 4821 } 4822 break; 4823 4824 default: 4825 /* xgettext:c-format */ 4826 (*info->fprintf_func) 4827 (info->stream, 4828 _("# internal disassembler error, unrecognised modifier (%c)"), 4829 type); 4830 abort (); 4831 } 4832 } 4833 4834 void 4835 print_mips_disassembler_options (FILE *stream) 4836 { 4837 unsigned int i; 4838 4839 fprintf (stream, _("\n\ 4840 The following MIPS specific disassembler options are supported for use\n\ 4841 with the -M switch (multiple options should be separated by commas):\n")); 4842 4843 fprintf (stream, _("\n\ 4844 gpr-names=ABI Print GPR names according to specified ABI.\n\ 4845 Default: based on binary being disassembled.\n")); 4846 4847 fprintf (stream, _("\n\ 4848 fpr-names=ABI Print FPR names according to specified ABI.\n\ 4849 Default: numeric.\n")); 4850 4851 fprintf (stream, _("\n\ 4852 cp0-names=ARCH Print CP0 register names according to\n\ 4853 specified architecture.\n\ 4854 Default: based on binary being disassembled.\n")); 4855 4856 fprintf (stream, _("\n\ 4857 hwr-names=ARCH Print HWR names according to specified\n\ 4858 architecture.\n\ 4859 Default: based on binary being disassembled.\n")); 4860 4861 fprintf (stream, _("\n\ 4862 reg-names=ABI Print GPR and FPR names according to\n\ 4863 specified ABI.\n")); 4864 4865 fprintf (stream, _("\n\ 4866 reg-names=ARCH Print CP0 register and HWR names according to\n\ 4867 specified architecture.\n")); 4868 4869 fprintf (stream, _("\n\ 4870 For the options above, the following values are supported for \"ABI\":\n\ 4871 ")); 4872 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 4873 fprintf (stream, " %s", mips_abi_choices[i].name); 4874 fprintf (stream, _("\n")); 4875 4876 fprintf (stream, _("\n\ 4877 For the options above, The following values are supported for \"ARCH\":\n\ 4878 ")); 4879 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 4880 if (*mips_arch_choices[i].name != '\0') 4881 fprintf (stream, " %s", mips_arch_choices[i].name); 4882 fprintf (stream, _("\n")); 4883 4884 fprintf (stream, _("\n")); 4885 } 4886 #endif 4887
