1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 1 3 4 #include "qemu-common.h" 5 6 /* CPU interfaces that are target independent. */ 7 8 #ifndef CONFIG_USER_ONLY 9 #include "exec/hwaddr.h" 10 #endif 11 12 #ifndef NEED_CPU_H 13 #include "exec/poison.h" 14 #endif 15 16 #include "qemu/bswap.h" 17 #include "qemu/queue.h" 18 19 /** 20 * CPUListState: 21 * @cpu_fprintf: Print function. 22 * @file: File to print to using @cpu_fprint. 23 * 24 * State commonly used for iterating over CPU models. 25 */ 26 typedef struct CPUListState { 27 fprintf_function cpu_fprintf; 28 FILE *file; 29 } CPUListState; 30 31 #if !defined(CONFIG_USER_ONLY) 32 33 enum device_endian { 34 DEVICE_NATIVE_ENDIAN, 35 DEVICE_BIG_ENDIAN, 36 DEVICE_LITTLE_ENDIAN, 37 }; 38 39 /* address in the RAM (different from a physical address) */ 40 #if defined(CONFIG_XEN_BACKEND) 41 typedef uint64_t ram_addr_t; 42 # define RAM_ADDR_MAX UINT64_MAX 43 # define RAM_ADDR_FMT "%" PRIx64 44 #else 45 typedef uintptr_t ram_addr_t; 46 # define RAM_ADDR_MAX UINTPTR_MAX 47 # define RAM_ADDR_FMT "%" PRIxPTR 48 #endif 49 50 /* memory API */ 51 52 /* MMIO pages are identified by a combination of an IO device index and 53 3 flags. The ROMD code stores the page ram offset in iotlb entry, 54 so only a limited number of ids are avaiable. */ 55 56 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) 57 58 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); 59 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); 60 61 void cpu_register_physical_memory_log(hwaddr start_addr, 62 ram_addr_t size, 63 ram_addr_t phys_offset, 64 ram_addr_t region_offset, 65 bool log_dirty); 66 67 static inline void cpu_register_physical_memory_offset(hwaddr start_addr, 68 ram_addr_t size, 69 ram_addr_t phys_offset, 70 ram_addr_t region_offset) 71 { 72 cpu_register_physical_memory_log(start_addr, size, phys_offset, 73 region_offset, false); 74 } 75 76 static inline void cpu_register_physical_memory(hwaddr start_addr, 77 ram_addr_t size, 78 ram_addr_t phys_offset) 79 { 80 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); 81 } 82 83 ram_addr_t cpu_get_physical_page_desc(hwaddr addr); 84 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, 85 ram_addr_t size, void *host); 86 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size); 87 void qemu_ram_free(ram_addr_t addr); 88 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 89 /* This should only be used for ram local to a device. */ 90 void *qemu_get_ram_ptr(ram_addr_t addr); 91 /* Same but slower, to use for migration, where the order of 92 * RAMBlocks must not change. */ 93 void *qemu_safe_ram_ptr(ram_addr_t addr); 94 /* This should not be used by devices. */ 95 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); 96 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 97 98 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, 99 CPUWriteMemoryFunc * const *mem_write, 100 void *opaque); 101 void cpu_unregister_io_memory(int table_address); 102 103 void cpu_physical_memory_rw(hwaddr addr, void *buf, 104 int len, int is_write); 105 static inline void cpu_physical_memory_read(hwaddr addr, 106 void *buf, int len) 107 { 108 cpu_physical_memory_rw(addr, buf, len, 0); 109 } 110 static inline void cpu_physical_memory_write(hwaddr addr, 111 const void *buf, int len) 112 { 113 cpu_physical_memory_rw(addr, (void*)buf, len, 1); 114 } 115 void *cpu_physical_memory_map(hwaddr addr, 116 hwaddr *plen, 117 int is_write); 118 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 119 int is_write, hwaddr access_len); 120 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); 121 122 uint32_t ldub_phys(hwaddr addr); 123 uint32_t lduw_le_phys(hwaddr addr); 124 uint32_t lduw_be_phys(hwaddr addr); 125 uint32_t ldl_le_phys(hwaddr addr); 126 uint32_t ldl_be_phys(hwaddr addr); 127 uint64_t ldq_le_phys(hwaddr addr); 128 uint64_t ldq_be_phys(hwaddr addr); 129 void stb_phys(hwaddr addr, uint32_t val); 130 void stw_le_phys(hwaddr addr, uint32_t val); 131 void stw_be_phys(hwaddr addr, uint32_t val); 132 void stl_le_phys(hwaddr addr, uint32_t val); 133 void stl_be_phys(hwaddr addr, uint32_t val); 134 void stq_le_phys(hwaddr addr, uint64_t val); 135 void stq_be_phys(hwaddr addr, uint64_t val); 136 137 #ifdef NEED_CPU_H 138 uint32_t lduw_phys(hwaddr addr); 139 uint32_t ldl_phys(hwaddr addr); 140 uint64_t ldq_phys(hwaddr addr); 141 void stl_phys_notdirty(hwaddr addr, uint32_t val); 142 void stq_phys_notdirty(hwaddr addr, uint64_t val); 143 void stw_phys(hwaddr addr, uint32_t val); 144 void stl_phys(hwaddr addr, uint32_t val); 145 void stq_phys(hwaddr addr, uint64_t val); 146 #endif 147 148 void cpu_physical_memory_write_rom(hwaddr addr, 149 const void *buf, int len); 150 151 #define IO_MEM_SHIFT 3 152 153 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ 154 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ 155 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) 156 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) 157 158 /* Acts like a ROM when read and like a device when written. */ 159 #define IO_MEM_ROMD (1) 160 #define IO_MEM_SUBPAGE (2) 161 #define IO_MEM_SUBWIDTH (4) 162 163 #endif 164 165 #endif /* !CPU_COMMON_H */ 166
