| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 89 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
99 int64_t Imm = MO.getImm();
103 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
107 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
111 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
149 int64_t Imm = MO.getImm();
153 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
156 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
223 int Imm = (int) MO.getImm();
225 if (Imm)
[all...] |
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.cpp | 162 uint64_t Imm = MI->getOperand(OpNum).getImm();
163 assert(Imm > 0 && Imm < 15 && "Invalid condition");
164 O << CondNames[Imm - 1];
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 88 IntFloatUnion Imm;
90 Imm.I = MO.getImm();
92 Imm.F = MO.getFPImm();
96 if (Imm.I >= 0 && Imm.I <= 64)
97 return 128 + Imm.I;
99 if (Imm.I >= -16 && Imm.I <= -1)
100 return 192 + abs(Imm.I);
102 if (Imm.F == 0.5f
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
66 switch (Imm) {
89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
90 switch (Imm) {
129 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
130 switch (Imm) {
169 O << markup("<imm:")
174 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
178 O << markup("<imm:")
219 << markup("<imm:"
[all...] |
| X86IntelInstPrinter.cpp | 55 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
56 switch (Imm) {
79 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
80 switch (Imm) {
119 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
120 switch (Imm) {
|
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg };
32 uint64_t Imm; // Integer immedate value.
105 OperandMap[BaseIdx + i].Kind = OpData::Imm;
106 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
234 case OpData::Imm:
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| CodeGenInstruction.h | 307 int64_t Imm;
316 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
325 int64_t getImm() const { assert(isImm()); return Imm; }
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 194 /// IMM = bits{8}
245 } Imm;
248 Imm.f = MO.getFPImm();
249 Value |= ((uint64_t)Imm.i) << 32;
|
| /external/llvm/lib/CodeGen/ |
| StackMaps.cpp | 90 int64_t Imm = (++MOI)->getImm();
91 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
98 int64_t Imm = (++MOI)->getImm();
99 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
105 int64_t Imm = MOI->getImm();
106 Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 223 int64_t Imm = MO.getImm();
224 O << '#' << Imm;
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| ARMMCCodeEmitter.cpp | 86 unsigned &Reg, unsigned &Imm,
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
536 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
539 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
561 Imm = SImm;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 86 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
323 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
327 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
333 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
362 int64_t Imm;
364 Imm = CI->getSExtValue();
366 Imm = CI->getZExtValue();
367 return Materialize32BitInt(Imm, RC);
370 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
[all...] |
| Mips16ISelLowering.cpp | 729 int64_t imm = MI->getOperand(1).getImm(); local
732 if (isUInt<8>(imm))
734 else if ((!ImmSigned && isUInt<16>(imm)) ||
735 (ImmSigned && isInt<16>(imm)))
740 .addImm(imm);
747 (unsigned shortOp, unsigned longOp, int64_t Imm) {
748 if (isUInt<8>(Imm))
750 else if (isInt<16>(Imm))
781 int64_t Imm = MI->getOperand(2).getImm();
782 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
[all...] |
| MipsSEISelDAGToDAG.cpp | 407 // Returns true and sets Imm if:
410 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
428 Imm = SplatValue;
436 // true and sets Imm if:
450 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
462 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
472 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
473 return selectVSplatCommon(N, Imm, false, 1);
477 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
478 return selectVSplatCommon(N, Imm, false, 2)
[all...] |
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
114 int32_t SImm = static_cast<int32_t>(Imm);
120 if (Imm == FloatToBits(1.0f) ||
121 Imm == FloatToBits(-1.0f) ||
122 Imm == FloatToBits(0.5f) ||
123 Imm == FloatToBits(-0.5f) ||
124 Imm == FloatToBits(2.0f) ||
125 Imm == FloatToBits(-2.0f) ||
126 Imm == FloatToBits(4.0f) ||
127 Imm == FloatToBits(-4.0f))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 515 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
516 int Offset = FIOffset + Imm;
517 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|