| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/builder/ |
| PayloadAlignmentTest.java | 35 import org.jf.dexlib2.Opcode;
53 implBuilder.addInstruction(new BuilderInstruction10x(Opcode.NOP));
63 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
70 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
79 Assert.assertEquals(instruction.getOpcode(), Opcode.MOVE);
82 Assert.assertEquals(instruction.getOpcode(), Opcode.NOP);
85 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
93 implBuilder.addInstruction(new BuilderInstruction31t(Opcode.FILL_ARRAY_DATA, 0, label));
94 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
95 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
177 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
184 Opcode = NewOpcode
[all...] |
| MipsNaClELFStreamer.cpp | 66 unsigned Opcode = MI.getOpcode();
70 switch (Opcode) {
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
207 switch (Opcode) {
|
| /external/smack/src/org/xbill/DNS/ |
| Opcode.java | 11 public final class Opcode {
30 private static Mnemonic opcodes = new Mnemonic("DNS Opcode",
46 Opcode() {}
48 /** Converts a numeric Opcode into a String */
54 /** Converts a String representation of an Opcode into its numeric value */
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 175 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
176 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
184 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
185 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| /external/chromium_org/third_party/WebKit/Source/core/xml/ |
| XPathPredicate.h | 69 enum Opcode {
72 NumericOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
78 Opcode m_opcode;
83 enum Opcode { OpcodeEqual, OpcodeNotEqual, OpcodeGreaterThan, OpcodeLessThan, OpcodeGreaterOrEqual, OpcodeLessOrEqual };
84 EqTestOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
91 Opcode m_opcode;
96 enum Opcode { OP_And, OP_Or };
97 LogicalOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
104 Opcode m_opcode;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 24 enum Opcode {
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
|
| /external/lldb/include/lldb/Core/ |
| Opcode.h | 1 //===-- Opcode.h ------------------------------------------------*- C++ -*-===//
28 class Opcode
42 Opcode () : m_type (eTypeInvalid)
46 Opcode (uint8_t inst) : m_type (eType8)
51 Opcode (uint16_t inst) : m_type (eType16)
56 Opcode (uint32_t inst) : m_type (eType32)
61 Opcode (uint64_t inst) : m_type (eType64)
66 Opcode (uint8_t *bytes, size_t length)
74 m_type = Opcode::eTypeInvalid;
76 Opcode::Typ
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 78 unsigned Opcode = MI->getOpcode();
80 switch(Opcode) {
104 if (Opcode == ARM::t2HINT)
168 if (Opcode == ARM::t2STMDB_UPD)
197 if (Opcode == ARM::t2LDMIA_UPD)
274 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
279 NewMI.setOpcode(Opcode);
813 unsigned Opcode = MI->getOpcode();
816 if (Opcode == ARM::t2MRS_M
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 96 unsigned Opcode = MI.getOpcode();
97 const MCInstrDesc &Desc = MCII.get(Opcode);
98 if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 84 unsigned Opcode = MI->getOpcode();
85 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
95 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| atifragshader.h | 24 GLenum opcode; member in struct:ati_fs_opcode_st
53 GLenum Opcode[2];
62 GLenum Opcode;
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 178 unsigned Opcode = Node->getOpcode();
196 switch(Opcode) {
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 305 unsigned Opcode = C->getOpcode();
306 switch (Opcode) {
348 if (Instruction::isBinaryOp(Opcode)) {
353 if (Instruction::isCast(Opcode)) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 278 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
333 unsigned Opcode = MI->getOpcode();
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
370 if (HasCTRSet && Opcode == PPC::BCTRL)
391 unsigned Opcode = MI->getOpcode();
394 GetInstrType(Opcode, isFirst, isSingle, isCracked,
399 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
|
| /external/llvm/lib/Target/R600/ |
| R600EmitClauseMarkers.cpp | 273 unsigned Opcode = PushBeforeModifier ?
275 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
|
| R600ExpandSpecialInstrs.cpp | 102 // The native opcode used by PRED_X is stored as an immediate in the
105 MI.getOperand(2).getImm(), // opcode
218 unsigned Opcode = BMI->getOpcode();
222 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
225 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
314 unsigned Opcode = MI.getOpcode();
315 switch (Opcode) {
317 Opcode = AMDGPU::CUBE_r600_real;
320 Opcode = AMDGPU::CUBE_eg_real;
327 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1)
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 36 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
|
