/external/llvm/lib/CodeGen/ |
AllocationOrder.cpp | 35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 44 dbgs() << ' ' << PrintReg(Hints[I], TRI);
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CriticalAntiDepBreaker.h | 38 const TargetRegisterInfo *TRI;
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DeadMachineInstructionElim.cpp | 33 const TargetRegisterInfo *TRI; 93 TRI = MF.getTarget().getRegisterInfo(); 154 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true); 170 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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RegAllocBase.h | 61 const TargetRegisterInfo *TRI; 69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
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ProcessImplicitDefs.cpp | 29 const TargetRegisterInfo *TRI; 107 !TRI->regsOverlap(Reg, UserReg)) 142 TRI = MF.getTarget().getRegisterInfo();
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AggressiveAntiDepBreaker.h | 50 /// (i.e. TRI->getNumRegs()). 121 const TargetRegisterInfo *TRI;
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BranchFolding.h | 30 const TargetRegisterInfo *tri, 91 const TargetRegisterInfo *TRI;
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ExpandPostRAPseudos.cpp | 32 const TargetRegisterInfo *TRI; 92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 185 TRI = MF.getTarget().getRegisterInfo();
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RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI; 62 CoalescerPair(const TargetRegisterInfo &tri) 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 69 const TargetRegisterInfo &tri) 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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/external/llvm/include/llvm/CodeGen/ |
StackMapLivenessAnalysis.h | 35 const TargetRegisterInfo *TRI;
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LivePhysRegs.h | 44 const TargetRegisterInfo *TRI; 51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} 54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { 55 assert(TRI && "Invalid TargetRegisterInfo pointer."); 56 LiveRegs.setUniverse(TRI->getNumRegs()); 62 TRI = _TRI; 64 LiveRegs.setUniverse(TRI->getNumRegs()); 75 assert(TRI && "LivePhysRegs is not initialized.") [all...] |
LiveStackAnalysis.h | 28 const TargetRegisterInfo *TRI;
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FastISel.h | 61 const TargetRegisterInfo &TRI;
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LiveRegMatrix.h | 40 const TargetRegisterInfo *TRI;
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LiveVariables.h | 132 const TargetRegisterInfo *TRI; 200 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound)) 236 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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ResourcePriorityQueue.h | 60 const TargetRegisterInfo *TRI;
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/external/llvm/lib/Target/Mips/ |
MipsFrameLowering.cpp | 104 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); 113 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { 114 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.h | 34 const TargetRegisterInfo *TRI;
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/external/llvm/lib/Target/AArch64/ |
AArch64DeadRegisterDefinitionsPass.cpp | 31 const TargetRegisterInfo *TRI; 55 if (TRI->regsOverlap(Reg, MO.getReg())) 122 TRI = MF.getTarget().getRegisterInfo();
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AArch64StorePairSuppress.cpp | 31 const TargetRegisterInfo *TRI; 122 TRI = MF->getTarget().getRegisterInfo(); 150 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
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/external/llvm/lib/Target/Hexagon/ |
HexagonCallingConvLower.cpp | 58 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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/external/llvm/lib/Target/R600/ |
SIFixSGPRLiveRanges.cpp | 76 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( 97 if (!TRI->isSGPRClass(RC))
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SILowerI1Copies.cpp | 75 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 117 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { 129 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 53 const R600RegisterInfo &TRI = TII->getRegisterInfo(); 105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 107 Src1 = TRI.getSubReg(Src1, SubRegIndex); 110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); 111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex) [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
AsmPrinterDwarf.cpp | 252 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 253 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); 264 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) { 265 Reg = TRI->getDwarfRegNum(*SR, false); 267 unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg()); 268 unsigned Size = TRI->getSubRegIdxSize(Idx); 269 unsigned Offset = TRI->getSubRegIdxOffset(Idx); 294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8; 298 for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) { 299 unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR) [all...] |