1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "config.h" 27 #include <setjmp.h> 28 #include <inttypes.h> 29 #include <signal.h> 30 #include "qemu-common.h" 31 #include "qemu/osdep.h" 32 #include "qemu/queue.h" 33 #include "exec/hwaddr.h" 34 35 #ifndef TARGET_LONG_BITS 36 #error TARGET_LONG_BITS must be defined before including this header 37 #endif 38 39 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 40 41 /* target_ulong is the type of a virtual address */ 42 #if TARGET_LONG_SIZE == 4 43 typedef int32_t target_long; 44 typedef uint32_t target_ulong; 45 #define TARGET_FMT_lx "%08x" 46 #define TARGET_FMT_ld "%d" 47 #define TARGET_FMT_lu "%u" 48 #elif TARGET_LONG_SIZE == 8 49 typedef int64_t target_long; 50 typedef uint64_t target_ulong; 51 #define TARGET_FMT_lx "%016" PRIx64 52 #define TARGET_FMT_ld "%" PRId64 53 #define TARGET_FMT_lu "%" PRIu64 54 #else 55 #error TARGET_LONG_SIZE undefined 56 #endif 57 58 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) 59 60 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 61 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 62 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 63 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 64 65 #define TB_JMP_CACHE_BITS 12 66 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 67 68 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for 69 addresses on the same page. The top bits are the same. This allows 70 TLB invalidation to quickly clear a subset of the hash table. */ 71 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) 72 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) 73 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) 74 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) 75 76 #if !defined(CONFIG_USER_ONLY) 77 #define CPU_TLB_BITS 8 78 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 79 80 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 81 #define CPU_TLB_ENTRY_BITS 4 82 #else 83 #define CPU_TLB_ENTRY_BITS 5 84 #endif 85 86 typedef struct CPUTLBEntry { 87 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 88 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 89 go directly to ram. 90 bit 3 : indicates that the entry is invalid 91 bit 2..0 : zero 92 */ 93 target_ulong addr_read; 94 target_ulong addr_write; 95 target_ulong addr_code; 96 /* Addend to virtual address to get host address. IO accesses 97 use the corresponding iotlb value. */ 98 uintptr_t addend; 99 /* padding to get a power of two size */ 100 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 101 (sizeof(target_ulong) * 3 + 102 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + 103 sizeof(uintptr_t))]; 104 } CPUTLBEntry; 105 106 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 107 108 #define CPU_COMMON_TLB \ 109 /* The meaning of the MMU modes is defined in the target code. */ \ 110 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 111 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 112 target_ulong tlb_flush_addr; \ 113 target_ulong tlb_flush_mask; 114 115 #else 116 117 #define CPU_COMMON_TLB 118 119 #endif 120 121 122 #ifdef HOST_WORDS_BIGENDIAN 123 typedef struct icount_decr_u16 { 124 uint16_t high; 125 uint16_t low; 126 } icount_decr_u16; 127 #else 128 typedef struct icount_decr_u16 { 129 uint16_t low; 130 uint16_t high; 131 } icount_decr_u16; 132 #endif 133 134 struct kvm_run; 135 struct KVMState; 136 struct qemu_work_item; 137 138 typedef struct CPUBreakpoint { 139 target_ulong pc; 140 int flags; /* BP_* */ 141 QTAILQ_ENTRY(CPUBreakpoint) entry; 142 } CPUBreakpoint; 143 144 typedef struct CPUWatchpoint { 145 target_ulong vaddr; 146 target_ulong len_mask; 147 int flags; /* BP_* */ 148 QTAILQ_ENTRY(CPUWatchpoint) entry; 149 } CPUWatchpoint; 150 151 #define CPU_TEMP_BUF_NLONGS 128 152 #define CPU_COMMON \ 153 struct TranslationBlock *current_tb; /* currently executing TB */ \ 154 /* soft mmu support */ \ 155 /* in order to avoid passing too many arguments to the MMIO \ 156 helpers, we store some rarely used information in the CPU \ 157 context) */ \ 158 uintptr_t mem_io_pc; /* host pc at which the memory was \ 159 accessed */ \ 160 target_ulong mem_io_vaddr; /* target virtual addr at which the \ 161 memory was accessed */ \ 162 CPU_COMMON_TLB \ 163 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ 164 \ 165 int64_t icount_extra; /* Instructions until next timer event. */ \ 166 /* Number of cycles left, with interrupt flag in high bit. \ 167 This allows a single read-compare-cbranch-write sequence to test \ 168 for both decrementer underflow and exceptions. */ \ 169 union { \ 170 uint32_t u32; \ 171 icount_decr_u16 u16; \ 172 } icount_decr; \ 173 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ 174 \ 175 /* from this point: preserved by CPU reset */ \ 176 /* ice debug support */ \ 177 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ 178 \ 179 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ 180 CPUWatchpoint *watchpoint_hit; \ 181 \ 182 /* Core interrupt code */ \ 183 jmp_buf jmp_env; \ 184 int exception_index; \ 185 \ 186 /* user data */ \ 187 void *opaque; \ 188 \ 189 190 #endif 191
