1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef _EXEC_ALL_H_ 21 #define _EXEC_ALL_H_ 22 23 #include "qemu-common.h" 24 #include "exec/cpu-common.h" 25 #include "exec/cpu-all.h" 26 27 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 28 #define DEBUG_DISAS 29 30 /* Page tracking code uses ram addresses in system mode, and virtual 31 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 32 type. */ 33 #if defined(CONFIG_USER_ONLY) 34 typedef abi_ulong tb_page_addr_t; 35 #else 36 typedef ram_addr_t tb_page_addr_t; 37 #endif 38 39 /* is_jmp field values */ 40 #define DISAS_NEXT 0 /* next instruction can be analyzed */ 41 #define DISAS_JUMP 1 /* only pc was modified dynamically */ 42 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ 43 #define DISAS_TB_JUMP 3 /* only pc was modified statically */ 44 45 struct TranslationBlock; 46 typedef struct TranslationBlock TranslationBlock; 47 48 /* XXX: make safe guess about sizes */ 49 #define MAX_OP_PER_INSTR 208 50 51 #if HOST_LONG_BITS == 32 52 #define MAX_OPC_PARAM_PER_ARG 2 53 #else 54 #define MAX_OPC_PARAM_PER_ARG 1 55 #endif 56 #define MAX_OPC_PARAM_IARGS 5 57 #define MAX_OPC_PARAM_OARGS 1 58 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) 59 60 /* A Call op needs up to 4 + 2N parameters on 32-bit archs, 61 * and up to 4 + N parameters on 64-bit archs 62 * (N = number of input arguments + output arguments). */ 63 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) 64 #define OPC_BUF_SIZE 2048 65 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) 66 67 /* Maximum size a TCG op can expand to. This is complicated because a 68 single op may require several host instructions and register reloads. 69 For now take a wild guess at 192 bytes, which should allow at least 70 a couple of fixup instructions per argument. */ 71 #define TCG_MAX_OP_SIZE 192 72 73 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) 74 75 #include "qemu/log.h" 76 77 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); 78 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb); 79 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 80 int pc_pos); 81 82 unsigned long code_gen_max_block_size(void); 83 void cpu_gen_init(void); 84 void tcg_exec_init(unsigned long tb_size); 85 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, 86 int *gen_code_size_ptr); 87 bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); 88 89 void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); 90 void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr); 91 TranslationBlock *tb_gen_code(CPUArchState *env, 92 target_ulong pc, target_ulong cs_base, int flags, 93 int cflags); 94 void cpu_exec_init(CPUArchState *env); 95 void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1); 96 int page_unprotect(target_ulong address, uintptr_t pc, void *puc); 97 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, 98 int is_cpu_write_access); 99 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, 100 int is_cpu_write_access); 101 #if !defined(CONFIG_USER_ONLY) 102 /* cputlb.c */ 103 void tlb_flush_page(CPUArchState *env, target_ulong addr); 104 void tlb_flush(CPUArchState *env, int flush_global); 105 void tlb_set_page(CPUArchState *env, target_ulong vaddr, 106 hwaddr paddr, int prot, 107 int mmu_idx, target_ulong size); 108 void tb_reset_jump_recursive(TranslationBlock *tb); 109 void tb_invalidate_phys_addr(hwaddr addr); 110 #else 111 static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) 112 { 113 } 114 115 static inline void tlb_flush(CPUArchState *env, int flush_global) 116 { 117 } 118 #endif 119 120 typedef struct PhysPageDesc { 121 /* offset in host memory of the page + io_index in the low bits */ 122 ram_addr_t phys_offset; 123 ram_addr_t region_offset; 124 } PhysPageDesc; 125 126 PhysPageDesc *phys_page_find(hwaddr index); 127 PhysPageDesc *phys_page_find_alloc(hwaddr index, int alloc); 128 129 int io_mem_watch; 130 131 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 132 133 #define CODE_GEN_PHYS_HASH_BITS 15 134 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) 135 136 /* estimated block size for TB allocation */ 137 /* XXX: use a per code average code fragment size and modulate it 138 according to the host CPU */ 139 #if defined(CONFIG_SOFTMMU) 140 #define CODE_GEN_AVG_BLOCK_SIZE 128 141 #else 142 #define CODE_GEN_AVG_BLOCK_SIZE 64 143 #endif 144 145 #if defined(__arm__) || defined(_ARCH_PPC) \ 146 || defined(__x86_64__) || defined(__i386__) \ 147 || defined(__sparc__) || defined(__aarch64__) \ 148 || defined(CONFIG_TCG_INTERPRETER) 149 #define USE_DIRECT_JUMP 150 #endif 151 152 struct TranslationBlock { 153 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 154 target_ulong cs_base; /* CS base for this block */ 155 uint64_t flags; /* flags defining in which context the code was generated */ 156 uint16_t size; /* size of target code for this block (1 <= 157 size <= TARGET_PAGE_SIZE) */ 158 uint16_t cflags; /* compile flags */ 159 #define CF_COUNT_MASK 0x7fff 160 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ 161 162 uint8_t *tc_ptr; /* pointer to the translated code */ 163 /* next matching tb for physical address. */ 164 struct TranslationBlock *phys_hash_next; 165 /* first and second physical page containing code. The lower bit 166 of the pointer tells the index in page_next[] */ 167 struct TranslationBlock *page_next[2]; 168 tb_page_addr_t page_addr[2]; 169 170 /* the following data are used to directly call another TB from 171 the code of this one. */ 172 uint16_t tb_next_offset[2]; /* offset of original jump target */ 173 #ifdef USE_DIRECT_JUMP 174 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ 175 #else 176 uintptr_t tb_next[2]; /* address of jump generated code */ 177 #endif 178 /* list of TBs jumping to this one. This is a circular list using 179 the two least significant bits of the pointers to tell what is 180 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = 181 jmp_first */ 182 struct TranslationBlock *jmp_next[2]; 183 struct TranslationBlock *jmp_first; 184 uint32_t icount; 185 }; 186 187 #include "exec/spinlock.h" 188 189 typedef struct TBContext TBContext; 190 191 struct TBContext { 192 193 TranslationBlock *tbs; 194 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; 195 int nb_tbs; 196 /* any access to the tbs or the page table must use this lock */ 197 spinlock_t tb_lock; 198 199 /* statistics */ 200 int tb_flush_count; 201 int tb_phys_invalidate_count; 202 203 int tb_invalidated_flag; 204 }; 205 206 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) 207 { 208 target_ulong tmp; 209 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); 210 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; 211 } 212 213 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) 214 { 215 target_ulong tmp; 216 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); 217 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) 218 | (tmp & TB_JMP_ADDR_MASK)); 219 } 220 221 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) 222 { 223 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); 224 } 225 226 void tb_free(TranslationBlock *tb); 227 void tb_flush(CPUArchState *env); 228 void tb_link_phys(TranslationBlock *tb, 229 target_ulong phys_pc, target_ulong phys_page2); 230 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 231 void tb_invalidate_phys_page_fast0(hwaddr start, int len); 232 233 extern uint8_t *code_gen_ptr; 234 extern int code_gen_max_blocks; 235 236 #if defined(USE_DIRECT_JUMP) 237 238 #if defined(CONFIG_TCG_INTERPRETER) 239 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 240 { 241 /* patch the branch destination */ 242 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); 243 /* no need to flush icache explicitly */ 244 } 245 #elif defined(_ARCH_PPC) 246 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); 247 #define tb_set_jmp_target1 ppc_tb_set_jmp_target 248 #elif defined(__i386__) || defined(__x86_64__) 249 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 250 { 251 /* patch the branch destination */ 252 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); 253 /* no need to flush icache explicitly */ 254 } 255 #elif defined(__aarch64__) 256 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 257 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target 258 #elif defined(__arm__) 259 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 260 { 261 #if !QEMU_GNUC_PREREQ(4, 1) 262 register unsigned long _beg __asm ("a1"); 263 register unsigned long _end __asm ("a2"); 264 register unsigned long _flg __asm ("a3"); 265 #endif 266 267 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ 268 *(uint32_t *)jmp_addr = 269 (*(uint32_t *)jmp_addr & ~0xffffff) 270 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); 271 272 #if QEMU_GNUC_PREREQ(4, 1) 273 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); 274 #else 275 /* flush icache */ 276 _beg = jmp_addr; 277 _end = jmp_addr + 4; 278 _flg = 0; 279 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); 280 #endif 281 } 282 #elif defined(__sparc__) 283 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); 284 #else 285 #error tb_set_jmp_target1 is missing 286 #endif 287 288 static inline void tb_set_jmp_target(TranslationBlock *tb, 289 int n, uintptr_t addr) 290 { 291 uint16_t offset = tb->tb_jmp_offset[n]; 292 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); 293 offset = tb->tb_jmp_offset[n + 2]; 294 if (offset != 0xffff) 295 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); 296 } 297 298 #else 299 300 /* set the jump target */ 301 static inline void tb_set_jmp_target(TranslationBlock *tb, 302 int n, uintptr_t addr) 303 { 304 tb->tb_next[n] = addr; 305 } 306 307 #endif 308 309 static inline void tb_add_jump(TranslationBlock *tb, int n, 310 TranslationBlock *tb_next) 311 { 312 /* NOTE: this test is only needed for thread safety */ 313 if (!tb->jmp_next[n]) { 314 /* patch the native jump address */ 315 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); 316 317 /* add in TB jmp circular list */ 318 tb->jmp_next[n] = tb_next->jmp_first; 319 tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); 320 } 321 } 322 323 /* GETRA is the true target of the return instruction that we'll execute, 324 defined here for simplicity of defining the follow-up macros. */ 325 #if defined(CONFIG_TCG_INTERPRETER) 326 extern uintptr_t tci_tb_ptr; 327 # define GETRA() tci_tb_ptr 328 #else 329 # define GETRA() \ 330 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 331 #endif 332 333 /* The true return address will often point to a host insn that is part of 334 the next translated guest insn. Adjust the address backward to point to 335 the middle of the call insn. Subtracting one would do the job except for 336 several compressed mode architectures (arm, mips) which set the low bit 337 to indicate the compressed mode; subtracting two works around that. It 338 is also the case that there are no host isas that contain a call insn 339 smaller than 4 bytes, so we don't worry about special-casing this. */ 340 #if defined(CONFIG_TCG_INTERPRETER) 341 # define GETPC_ADJ 0 342 #else 343 # define GETPC_ADJ 2 344 #endif 345 346 #define GETPC() (GETRA() - GETPC_ADJ) 347 348 #if !defined(CONFIG_USER_ONLY) 349 350 void phys_mem_set_alloc(void *(*alloc)(size_t)); 351 352 TranslationBlock *tb_find_pc(uintptr_t pc_ptr); 353 354 uint64_t io_mem_read(int index, hwaddr addr, unsigned size); 355 void io_mem_write(int index, hwaddr addr, uint64_t value, unsigned size); 356 357 extern CPUWriteMemoryFunc *_io_mem_write[IO_MEM_NB_ENTRIES][4]; 358 extern CPUReadMemoryFunc *_io_mem_read[IO_MEM_NB_ENTRIES][4]; 359 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; 360 361 void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, 362 uintptr_t retaddr); 363 364 uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 365 uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 366 uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 367 uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 368 369 #define ACCESS_TYPE (NB_MMU_MODES + 1) 370 #define MEMSUFFIX _code 371 372 #define DATA_SIZE 1 373 #include "exec/softmmu_header.h" 374 375 #define DATA_SIZE 2 376 #include "exec/softmmu_header.h" 377 378 #define DATA_SIZE 4 379 #include "exec/softmmu_header.h" 380 381 #define DATA_SIZE 8 382 #include "exec/softmmu_header.h" 383 384 #undef ACCESS_TYPE 385 #undef MEMSUFFIX 386 387 #endif 388 389 #if defined(CONFIG_USER_ONLY) 390 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 391 { 392 return addr; 393 } 394 #else 395 /* cputlb.c */ 396 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 397 #endif 398 399 typedef void (CPUDebugExcpHandler)(CPUArchState *env); 400 401 void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); 402 403 /* vl.c */ 404 extern int singlestep; 405 406 /* cpu-exec.c */ 407 extern volatile sig_atomic_t exit_request; 408 409 /* Deterministic execution requires that IO only be performed on the last 410 instruction of a TB so that interrupts take effect immediately. */ 411 static inline int can_do_io(CPUArchState *env) 412 { 413 if (!use_icount) { 414 return 1; 415 } 416 /* If not executing code then assume we are ok. */ 417 if (env->current_tb == NULL) { 418 return 1; 419 } 420 return env->can_do_io != 0; 421 } 422 423 #endif 424
