1 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the general parts of a Subtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/CommandLine.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/Target/TargetSubtargetInfo.h" 17 using namespace llvm; 18 19 //--------------------------------------------------------------------------- 20 // TargetSubtargetInfo Class 21 // 22 TargetSubtargetInfo::TargetSubtargetInfo() {} 23 24 TargetSubtargetInfo::~TargetSubtargetInfo() {} 25 26 // Temporary option to compare overall performance change when moving from the 27 // SD scheduler to the MachineScheduler pass pipeline. This is convenient for 28 // benchmarking during the transition from SD to MI scheduling. Once armv7 makes 29 // the switch, it should go away. The normal way to enable/disable the 30 // MachineScheduling pass itself is by using -enable-misched. For targets that 31 // already use MI sched (via MySubTarget::enableMachineScheduler()) 32 // -misched-bench=false negates the subtarget hook. 33 static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden, 34 cl::desc("Migrate from the target's default SD scheduler to MI scheduler")); 35 36 bool TargetSubtargetInfo::useMachineScheduler() const { 37 if (BenchMachineSched.getNumOccurrences()) 38 return BenchMachineSched; 39 return enableMachineScheduler(); 40 } 41 42 bool TargetSubtargetInfo::enableAtomicExpandLoadLinked() const { 43 return true; 44 } 45 46 bool TargetSubtargetInfo::enableMachineScheduler() const { 47 return false; 48 } 49 50 bool TargetSubtargetInfo::enableRALocalReassignment( 51 CodeGenOpt::Level OptLevel) const { 52 return true; 53 } 54 55 bool TargetSubtargetInfo::enablePostMachineScheduler() const { 56 return false; 57 } 58 59 bool TargetSubtargetInfo::enablePostRAScheduler( 60 CodeGenOpt::Level OptLevel, 61 AntiDepBreakMode& Mode, 62 RegClassVector& CriticalPathRCs) const { 63 Mode = ANTIDEP_NONE; 64 CriticalPathRCs.clear(); 65 return false; 66 } 67 68 bool TargetSubtargetInfo::useAA() const { 69 return false; 70 } 71
