1 ; Tests for SSE1 and below, without SSE2+. 2 ; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s 3 ; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s 4 5 define <8 x i16> @test1(<8 x i32> %a) nounwind { 6 ; CHECK: test1 7 ret <8 x i16> zeroinitializer 8 } 9 10 define <8 x i16> @test2(<8 x i32> %a) nounwind { 11 ; CHECK: test2 12 %c = trunc <8 x i32> %a to <8 x i16> ; <<8 x i16>> [#uses=1] 13 ret <8 x i16> %c 14 } 15 16 ; PR7993 17 ;define <4 x i32> @test3(<4 x i16> %a) nounwind { 18 ; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1] 19 ; ret <4 x i32> %c 20 ;} 21 22 ; This should not emit shuffles to populate the top 2 elements of the 4-element 23 ; vector that this ends up returning. 24 ; rdar://8368414 25 define <2 x float> @test4(<2 x float> %A, <2 x float> %B) nounwind { 26 entry: 27 %tmp7 = extractelement <2 x float> %A, i32 0 28 %tmp5 = extractelement <2 x float> %A, i32 1 29 %tmp3 = extractelement <2 x float> %B, i32 0 30 %tmp1 = extractelement <2 x float> %B, i32 1 31 %add.r = fadd float %tmp7, %tmp3 32 %add.i = fsub float %tmp5, %tmp1 33 %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0 34 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1 35 ret <2 x float> %tmp9 36 ; CHECK-LABEL: test4: 37 ; CHECK-NOT: shufps $16 38 ; CHECK: shufps $1, 39 ; CHECK-NOT: shufps $16 40 ; CHECK: shufps $1, 41 ; CHECK-NOT: shufps $16 42 ; CHECK: unpcklps 43 ; CHECK-NOT: shufps $16 44 ; CHECK: ret 45 } 46 47 ; We used to get stuck in type legalization for this example when lowering the 48 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type) 49 ; is not. We used to ping pong between splitting the vselect for the v4i 50 ; condition operand and widening the resulting vselect for the v4f32 result. 51 ; PR18036 52 53 ; CHECK-LABEL: vselect 54 define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) { 55 entry: 56 %a1 = icmp eq <4 x i32> %q, zeroinitializer 57 %a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer 58 ret <4 x float> %a14 59 } 60
