/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 166 mMips->ADDIU(R_sp, R_sp, -(5 * 4)); 184 mMips->ADDIU(R_sp, R_sp, (5 * 4)); 446 mMips->ADDIU(Rd, Rn, src); 784 mMips->ADDIU(Rn, Rn, amode.value); 792 mMips->ADDIU(Rn, Rn, amode.value); 815 mMips->ADDIU(Rn, Rn, amode.value); 820 mMips->ADDIU(Rn, Rn, amode.value); 848 mMips->ADDIU(Rn, Rn, amode.value); 857 mMips->ADDIU(Rn, Rn, amode.value); // post index always writes back 880 mMips->ADDIU(Rn, Rn, amode.value) [all...] |
MIPSAssembler.h | 273 void ADDIU(int Rt, int Rs, int16_t imm);
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/external/chromium_org/v8/src/mips/ |
constants-mips.cc | 295 case ADDIU:
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constants-mips.h | 275 ADDIU = ((1 << 3) + 1) << kOpcodeShift, 590 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 593 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
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assembler-mips.cc | 249 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 251 const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift) 254 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. 255 const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift) 618 return ((instr & kOpcodeMask) == ADDIU); 1196 void Assembler::addiu(Register rd, Register rs, int32_t j) { function in class:v8::Assembler [all...] |
simulator-mips.cc | [all...] |
/external/valgrind/main/none/tests/mips64/ |
arithmetic_instruction.c | 6 ADD=0, ADDI, ADDIU, ADDU, 45 case ADDIU: 49 TEST2("addiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 50 TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 51 TEST2("addiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 52 TEST2("addiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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