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Searched
refs:CTX_RB3D_CNTL
(Results
1 - 12
of
12
) sorted by null
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_state_init.c
334
atom->cmd[
CTX_RB3D_CNTL
] &= ~(0xf << 10);
336
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888;
339
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565;
342
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB4444;
345
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB1555;
387
OUT_BATCH(atom->cmd[
CTX_RB3D_CNTL
]);
703
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = (RADEON_PLANE_MASK_ENABLE |
708
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_DITHER_INIT;
711
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_SCALE_DITHER_ENABLE;
721
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
[
all
...]
radeon_state.c
142
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE;
144
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE;
[
all
...]
radeon_context.h
99
#define
CTX_RB3D_CNTL
10
/external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state_init.c
334
atom->cmd[
CTX_RB3D_CNTL
] &= ~(0xf << 10);
336
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888;
339
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565;
342
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB4444;
345
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB1555;
387
OUT_BATCH(atom->cmd[
CTX_RB3D_CNTL
]);
703
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = (RADEON_PLANE_MASK_ENABLE |
708
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_DITHER_INIT;
711
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_SCALE_DITHER_ENABLE;
721
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
[
all
...]
radeon_state.c
142
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] |= RADEON_ROP_ENABLE;
144
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] &= ~RADEON_ROP_ENABLE;
[
all
...]
radeon_context.h
99
#define
CTX_RB3D_CNTL
10
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_state.c
205
GLuint cntl = rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] &
218
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl | R200_ROP_ENABLE;
223
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
226
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl;
682
GLuint flag = rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] & ~R200_PLANE_MASK_ENABLE;
697
if ( rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] != flag ) {
699
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = flag;
[
all
...]
r200_state_init.c
451
atom->cmd[
CTX_RB3D_CNTL
] &= ~(0xf << 10);
453
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888;
456
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565;
459
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB4444;
462
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB1555;
505
OUT_BATCH(atom->cmd[
CTX_RB3D_CNTL
]);
[
all
...]
r200_context.h
108
#define
CTX_RB3D_CNTL
10
/external/mesa3d/src/mesa/drivers/dri/r200/
r200_state.c
205
GLuint cntl = rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] &
218
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl | R200_ROP_ENABLE;
223
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
226
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = cntl;
682
GLuint flag = rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] & ~R200_PLANE_MASK_ENABLE;
697
if ( rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] != flag ) {
699
rmesa->hw.ctx.cmd[
CTX_RB3D_CNTL
] = flag;
[
all
...]
r200_state_init.c
451
atom->cmd[
CTX_RB3D_CNTL
] &= ~(0xf << 10);
453
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888;
456
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565;
459
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB4444;
462
atom->cmd[
CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB1555;
505
OUT_BATCH(atom->cmd[
CTX_RB3D_CNTL
]);
[
all
...]
r200_context.h
108
#define
CTX_RB3D_CNTL
10
Completed in 54 milliseconds