| /external/clang/test/SemaTemplate/ |
| value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) {
6 return Cond? "honk" : N;
9 const char *f1(bool Cond) {
10 return Cond? N : "honk";
|
| /ndk/tests/device/issue42891-boost-1_52/jni/boost/boost/utility/ |
| enable_if.hpp | 35 template <class Cond, class T = void>
36 struct enable_if : public enable_if_c<Cond::value, T> {};
46 template <class Cond, class T>
47 struct lazy_enable_if : public lazy_enable_if_c<Cond::value, T> {};
58 template <class Cond, class T = void>
59 struct disable_if : public disable_if_c<Cond::value, T> {};
69 template <class Cond, class T>
70 struct lazy_disable_if : public lazy_disable_if_c<Cond::value, T> {};
99 template <class Cond, class T = detail::enable_if_default_T>
103 template <class Cond, class T = detail::enable_if_default_T>
[all...] |
| /external/chromium_org/sandbox/linux/seccomp-bpf-helpers/ |
| syscall_parameters_restrictions.cc | 80 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
83 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_HAS_ANY_BITS,
94 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
97 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
100 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_HAS_ANY_BITS,
110 return sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
112 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
114 sandbox->Cond(0, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL,
120 return sandbox->Cond(1, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, TCGETS,
122 sandbox->Cond(1, ErrorCode::TP_32BIT, ErrorCode::OP_EQUAL, FIONREAD
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const {
80 Cond.push_back(MachineOperand::CreateImm(Opc));
83 Cond.push_back(Inst->getOperand(i));
89 SmallVectorImpl<MachineOperand> &Cond,
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99 const SmallVectorImpl<MachineOperand>& Cond)
101 unsigned Opc = Cond[0].getImm();
105 for (unsigned i = 1; i < Cond.size(); ++i) {
106 if (Cond[i].isReg())
107 MIB.addReg(Cond[i].getReg())
[all...] |
| MipsInstrInfo.h | 56 SmallVectorImpl<MachineOperand> &Cond,
63 const SmallVectorImpl<MachineOperand> &Cond,
67 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
71 SmallVectorImpl<MachineOperand> &Cond,
136 SmallVectorImpl<MachineOperand> &Cond) const;
139 const SmallVectorImpl<MachineOperand>& Cond) const;
|
| /external/chromium_org/components/nacl/loader/nonsfi/ |
| nonsfi_sandbox.cc | 59 return sb->Cond(1, ErrorCode::TP_32BIT,
61 sb->Cond(2, mask_long_type,
65 sb->Cond(1, ErrorCode::TP_32BIT,
68 sb->Cond(1, ErrorCode::TP_32BIT,
70 sb->Cond(2, mask_long_type,
84 ErrorCode result = sb->Cond(0, ErrorCode::TP_32BIT,
87 sb->Cond(0, ErrorCode::TP_32BIT,
90 sb->Cond(0, ErrorCode::TP_32BIT,
93 sb->Cond(0, ErrorCode::TP_32BIT,
99 result = sb->Cond(0, ErrorCode::TP_32BIT
[all...] |
| /ndk/tests/device/issue42891-boost-1_52/jni/boost/boost/iterator/detail/ |
| enable_if.hpp | 66 template <class Cond,
70 : enabled<(Cond::value)>::template base<Return>
|
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| ConstraintManager.h | 68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) {
76 ProgramStateRef StTrue = assume(State, Cond, true);
78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
86 assert(assume(State, Cond, false) && "System is over constrained.");
91 ProgramStateRef StFalse = assume(State, Cond, false);
|
| /external/clang/test/SemaCXX/ |
| vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e,
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16;
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16;
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e;
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e;
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e;
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e;
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e;
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e;
55 (void)(Cond? c16 : ll16)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_loops.h | 12 struct rc_instruction * Cond;
|
| radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File,
200 loop->Cond->U.I.SrcReg[0].Index)){
201 limit = &loop->Cond->U.I.SrcReg[0];
202 counter = &loop->Cond->U.I.SrcReg[1];
204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File,
205 loop->Cond->U.I.SrcReg[1].Index)){
206 limit = &loop->Cond->U.I.SrcReg[1];
207 counter = &loop->Cond->U.I.SrcReg[0];
285 switch(loop->Cond->U.I.Opcode){
309 rc_remove_instruction(loop->Cond);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_loops.h | 12 struct rc_instruction * Cond;
|
| radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File,
200 loop->Cond->U.I.SrcReg[0].Index)){
201 limit = &loop->Cond->U.I.SrcReg[0];
202 counter = &loop->Cond->U.I.SrcReg[1];
204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File,
205 loop->Cond->U.I.SrcReg[1].Index)){
206 limit = &loop->Cond->U.I.SrcReg[1];
207 counter = &loop->Cond->U.I.SrcReg[0];
285 switch(loop->Cond->U.I.Opcode){
309 rc_remove_instruction(loop->Cond);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
80 SmallVectorImpl<MachineOperand> &Cond,
86 const SmallVectorImpl<MachineOperand> &Cond,
|
| MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
157 Cond[0].setImm(CC);
175 SmallVectorImpl<MachineOperand> &Cond,
210 Cond.clear();
234 if (Cond.empty()) {
237 Cond.push_back(MachineOperand::CreateImm(BranchCode));
243 assert(Cond.size() == 1);
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond,
60 const SmallVectorImpl<MachineOperand> &Cond,
83 SmallVectorImpl<MachineOperand> &Cond) const override;
|
| XCoreInstrInfo.cpp | 196 SmallVectorImpl<MachineOperand> &Cond,
229 Cond.push_back(MachineOperand::CreateImm(BranchCode));
230 Cond.push_back(LastInst->getOperand(0));
251 Cond.push_back(MachineOperand::CreateImm(BranchCode));
252 Cond.push_back(SecondLastInst->getOperand(0));
284 const SmallVectorImpl<MachineOperand> &Cond,
288 assert((Cond.size() == 2 || Cond.size() == 0) &&
292 if (Cond.empty()) {
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm())
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 69 DefinedSVal Cond,
72 if (Optional<Loc> LV = Cond.getAs<Loc>()) {
81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>();
84 return assume(state, Cond.castAs<NonLoc>(), Assumption);
88 NonLoc cond,
90 state = assumeAux(state, cond, assumption);
92 return SU->processAssume(state, cond, assumption);
115 NonLoc Cond,
120 if (!canReasonAbout(Cond)) {
122 SymbolRef sym = Cond.getAsSymExpr()
[all...] |
| SimpleConstraintManager.h | 36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
88 NonLoc Cond,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 127 SmallVectorImpl<MachineOperand> &Cond,
132 const SmallVectorImpl<MachineOperand> &Cond,
135 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
137 const SmallVectorImpl<MachineOperand> &Cond, unsigned,
141 const SmallVectorImpl<MachineOperand> &Cond,
160 const SmallVectorImpl<MachineOperand> &Cond) const;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
189 Cond.push_back(LastInst->getOperand(0));
207 Cond.push_back(SecondLastInst->getOperand(0));
253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
256 assert((Cond.size() == 1 || Cond.size() == 0) &&
261 if (Cond.empty()) // Unconditional branch
264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
|
| NVPTXInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
69 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
|
| /external/chromium_org/sandbox/linux/seccomp-bpf/ |
| sandbox_bpf_unittest.cc | 314 return sandbox->Cond(0,
337 return sandbox->Cond(0,
849 // Simple test demonstrating how to use SandboxBPF::Cond()
873 return sandbox->Cond(2,
883 return sandbox->Cond(1,
893 return sandbox->Cond(0,
898 sandbox->Cond(0,
923 // This test exercises the SandboxBPF::Cond() method by building a complex
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 68 SmallVectorImpl<MachineOperand> &Cond,
75 const SmallVectorImpl<MachineOperand> &Cond,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond,
216 Cond.push_back(predSet->getOperand(1));
217 Cond.push_back(predSet->getOperand(2));
218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
240 Cond.push_back(predSet->getOperand(1));
241 Cond.push_back(predSet->getOperand(2));
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
264 const SmallVectorImpl<MachineOperand> &Cond,
270 if (Cond.empty()) {
277 PredSet->getOperand(2).setImm(Cond[1].getImm())
[all...] |
