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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUSubtarget.h 40 InstrItineraryData InstrItins;
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
AMDGPUTargetMachine.h 37 const InstrItineraryData* InstrItins;
62 return InstrItins;
AMDGPUSubtarget.cpp 25 InstrItins = getInstrItineraryForCPU(CPU);
AMDGPUTargetMachine.cpp 54 InstrItins(&Subtarget.getInstrItineraryData()),
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUSubtarget.h 40 InstrItineraryData InstrItins;
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
AMDGPUTargetMachine.h 37 const InstrItineraryData* InstrItins;
62 return InstrItins;
AMDGPUSubtarget.cpp 25 InstrItins = getInstrItineraryForCPU(CPU);
AMDGPUTargetMachine.cpp 54 InstrItins(&Subtarget.getInstrItineraryData()),
  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 36 InstrItineraryData InstrItins;
77 return &InstrItins;
DFAPacketizer.h 46 const InstrItineraryData *InstrItins;
82 const InstrItineraryData *getInstrItins() const { return InstrItins; }
ResourcePriorityQueue.h 63 const InstrItineraryData* InstrItins;
  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 36 return EnableSchedItins && !InstrItins.isEmpty();
60 STI->initInstrItins(InstrItins);
80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
170 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
179 // Rather than directly querying InstrItins stage latency, we call a TII
181 // applicable to the InstrItins model. InstrSchedModel should model all
235 return TII->getInstrLatency(&InstrItins, MI)
    [all...]
DFAPacketizer.cpp 36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
  /external/llvm/lib/Target/Hexagon/
HexagonSubtarget.h 53 InstrItineraryData InstrItins;
61 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
HexagonSubtarget.cpp 82 InstrItins = getInstrItineraryForCPU(CPUString);
  /external/llvm/lib/Target/R600/
AMDGPUSubtarget.h 60 InstrItineraryData InstrItins;
70 return InstrItins;
AMDGPUTargetMachine.h 34 const InstrItineraryData *InstrItins;
60 return InstrItins;
AMDGPUSubtarget.cpp 44 InstrItins(getInstrItineraryForCPU(GPU)) {
  /external/llvm/lib/MC/
MCSubtargetInfo.cpp 113 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
114 InstrItins =
  /external/llvm/lib/Target/PowerPC/
PPCSubtarget.h 74 InstrItineraryData InstrItins;
146 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
  /external/llvm/include/llvm/MC/
MCSubtargetInfo.h 134 void initInstrItins(InstrItineraryData &InstrItins) const;
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 40 const InstrItineraryData *InstrItins;
  /external/llvm/lib/Target/ARM/
ARMSubtarget.h 231 InstrItineraryData InstrItins;
447 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
  /external/llvm/lib/Target/Mips/
MipsSubtarget.h 136 InstrItineraryData InstrItins;
257 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
  /external/llvm/lib/Target/X86/
X86Subtarget.h 214 InstrItineraryData InstrItins;
467 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }

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