/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 266 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 281 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 360 unsigned Op1, Op2; 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 365 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 373 unsigned Op1, Op2; 374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 378 Inst.addOperand(MCOperand::CreateImm(Op1)); [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineMulDivRem.cpp | 121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 126 if (Value *V = SimplifyMulInst(Op0, Op1, DL)) 132 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X 165 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { 191 if (isa<Constant>(Op1)) { 206 Value *Mul = Builder->CreateMul(C1, Op1); 210 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul); 216 if (Value *Op1v = dyn_castNegVal(Op1)) 222 Value *Op1C = Op1; 228 BO = dyn_cast<BinaryOperator>(Op1); [all...] |
InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 38 if (Constant *CUI = dyn_cast<Constant>(Op1)) 46 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { 50 Op1->getName()); 314 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, 319 if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1)) 321 else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1)) 324 COp1 = dyn_cast<ConstantInt>(Op1); [all...] |
InstCombineCompares.cpp | [all...] |
InstCombineAddSub.cpp | [all...] |
InstCombineAndOrXor.cpp | 801 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); 804 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); [all...] |
InstructionCombining.cpp | 216 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1)); 249 if (Op1 && Op1->getOpcode() == Opcode) { 251 Value *B = Op1->getOperand(0); 252 Value *C = Op1->getOperand(1); 291 if (Op1 && Op1->getOpcode() == Opcode) { 293 Value *B = Op1->getOperand(0); 294 Value *C = Op1->getOperand(1); 312 if (Op0 && Op1 & [all...] |
/external/llvm/lib/Analysis/ |
InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) 161 if (Op1->getOpcode() == OpcodeToExpand) { 163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); 197 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); 219 if (Op1 && Op1->getOpcode() == Opcode) { 221 Value *B = Op1->getOperand(0); 222 Value *C = Op1->getOperand(1); 261 if (Op1 && Op1->getOpcode() == Opcode) [all...] |
ConstantFolding.cpp | 612 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression. 617 Constant *Op1, const DataLayout *DL){ 630 computeKnownBits(Op1, KnownZero1, KnownOne1, DL); 636 // All the bits of Op1 that the 'and' could be masking are already zero. 637 return Op1; 654 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) && [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreSelectionDAGInfo.h | 31 SDValue Op1, SDValue Op2,
|
/external/llvm/include/llvm/Target/ |
TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2,
|
/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 54 SDValue Op1, SDValue Op2,
|
/external/llvm/include/llvm/CodeGen/ |
FastISel.h | 201 unsigned Op1, bool Op1IsKill); 228 unsigned Op1, bool Op1IsKill, 272 unsigned Op1, bool Op1IsKill); 279 unsigned Op1, bool Op1IsKill, 307 unsigned Op1, bool Op1IsKill, 315 unsigned Op1, bool Op1IsKill,
|
ISDOpcodes.h | [all...] |
SelectionDAG.h | 606 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, 611 Ops.push_back(Op1); [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 202 SDValue Op0, Op1; 206 if (!SelectADDRrr(Op, Op0, Op1)) 207 SelectADDRri(Op, Op0, Op1); 212 OutOps.push_back(Op1);
|
/external/llvm/lib/Transforms/Scalar/ |
Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 371 Scatterer Op1 = scatter(&I, I.getOperand(1)); 373 assert(Op1.size() == NumElems && "Mismatched binary operation"); 377 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 390 Scatterer Op1 = scatter(&SI, SI.getOperand(1)) [all...] |
CorrelatedValuePropagation.cpp | 169 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1)); 170 if (!Op1) return false; 176 C->getOperand(0), Op1, *PI, C->getParent()); 182 C->getOperand(0), Op1, *PI, C->getParent());
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | 386 unsigned Op1 = getRegForValue(I->getOperand(1)); 387 if (Op1 == 0) return false; 391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 447 unsigned Op1 = getRegForValue(I->getOperand(1)); 448 if (Op1 == 0) 458 Op1, Op1IsKill); [all...] |
LegalizeVectorOps.cpp | 671 SDValue Op1 = Op.getOperand(1); 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 707 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 714 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 848 SDValue Op1 = Op.getOperand(1); 863 TLI.getBooleanContents(Op1.getValueType()) != 870 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits() [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 173 ICToken Op1 = OperandStack.pop_back_val(); 179 Val = Op1.second + Op2.second; 183 Val = Op1.second - Op2.second; 187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 189 Val = Op1.second * Op2.second; 193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 196 Val = Op1.second / Op2.second; 200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 202 Val = Op1.second | Op2.second; 206 assert (Op1.first == IC_IMM && Op2.first == IC_IMM & [all...] |
/external/llvm/include/llvm/Analysis/ |
InstructionSimplify.h | 134 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 141 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 148 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397 // between the base and index. Try to fold Op1 into AM's displacement. 399 SDValue Op0, uint64_t Op1) { 401 int64_t TestDisp = AM.Disp + Op1; 423 SDValue Op1 = N.getOperand(1); 426 unsigned Op1Code = Op1->getOpcode(); 429 return expandAdjDynAlloc(AM, IsBase, Op1); 434 return expandDisp(AM, IsBase, Op1, 438 cast<ConstantSDNode>(Op1)->getSExtValue()); 440 if (IsBase && expandIndex(AM, Op0, Op1)) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 416 SDValue Op1 = N->getOperand(1); 421 CurDAG->computeKnownBits(Op1, RKZ, RKO); 428 unsigned Op1Opc = Op1.getOpcode(); 438 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 439 Op1.getOperand(0).getOpcode() != ISD::SRL) { 440 std::swap(Op0, Op1); 446 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 447 Op1.getOperand(0).getOpcode() != ISD::SRL) { 448 std::swap(Op0, Op1); 459 isInt32Immediate(Op1.getOperand(1), Value)) [all...] |