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Searched
refs:Orders
(Results
1 - 5
of
5
) sorted by null
/external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp
702
SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &
Orders
,
719
Orders
.push_back(std::make_pair(DVOrder, DbgMI));
733
SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &
Orders
,
739
ProcessSDDbgValues(N, DAG, Emitter,
Orders
, VRBaseMap, 0);
749
Orders
.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
753
Orders
.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos())));
754
ProcessSDDbgValues(N, DAG, Emitter,
Orders
, VRBaseMap, Order);
802
SmallVector<std::pair<unsigned, MachineInstr*>, 32>
Orders
;
842
ProcessSourceNode(N, DAG, Emitter, VRBaseMap,
Orders
, Seen);
849
ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap,
Orders
,
[
all
...]
/external/llvm/utils/TableGen/
CodeGenRegisters.h
244
// Allocation
orders
. Order[0] always contains all registers in Members.
245
std::vector<SmallVector<Record*, 16> >
Orders
;
352
return
Orders
[No];
355
// Return the total number of allocation
orders
available.
356
unsigned getNumOrders() const { return
Orders
.size(); }
CodeGenRegisters.cpp
686
Orders
.resize(1 + AltOrders->size());
690
Orders
[0].push_back((*Elements)[i]);
696
// Alternative allocation
orders
may be subsets.
700
Orders
[1 + i].append(Order.begin(), Order.end());
757
// Copy all allocation
orders
, filter out foreign registers from the larger
759
Orders
.resize(Super.
Orders
.size());
760
for (unsigned i = 0, ie = Super.
Orders
.size(); i != ie; ++i)
761
for (unsigned j = 0, je = Super.
Orders
[i].size(); j != je; ++j)
762
if (contains(RegBank.getReg(Super.
Orders
[i][j]))
[
all
...]
/external/chromium_org/ui/file_manager/file_manager/background/js/
volume_manager.js
283
*
Orders
two volumes by volumeType and volumeId.
/external/clang/lib/CodeGen/
CGBuiltin.cpp
[
all
...]
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