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Searched
refs:RegIdx
(Results
1 - 9
of
9
) sorted by null
/external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp
374
struct RegIdxOp
RegIdx
;
387
Op->
RegIdx
.Index = Index;
388
Op->
RegIdx
.RegInfo = RegInfo;
389
Op->
RegIdx
.Kind = RegKind;
399
assert(isRegIdx() && (
RegIdx
.Kind & RegKind_GPR) && "Invalid access!");
400
AsmParser.WarnIfAssemblerTemporary(
RegIdx
.Index, StartLoc);
402
return
RegIdx
.RegInfo->getRegClass(ClassID).getRegister(
RegIdx
.Index);
408
assert(isRegIdx() && (
RegIdx
.Kind & RegKind_GPR) && "Invalid access!");
410
return
RegIdx
.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index)
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/external/llvm/lib/CodeGen/
SplitKit.h
277
/// intervals. Given a pair (
RegIdx
, ParentVNI->id), Values contains:
279
/// 1. No entry - the value is not mapped to Edit.get(
RegIdx
).
281
/// Edit.get(
RegIdx
). Each value is represented by a minimal live range at
283
/// of
RegIdx
in RegAssign.
295
/// getLRCalc - Return the LRCalc to use for
RegIdx
. In spill mode, the
298
LiveRangeCalc &getLRCalc(unsigned
RegIdx
) {
299
return LRCalc[SpillMode != SM_Partition &&
RegIdx
!= 0];
302
/// defValue - define a value in
RegIdx
from ParentVNI at Idx.
307
VNInfo *defValue(unsigned
RegIdx
, const VNInfo *ParentVNI, SlotIndex Idx);
309
/// forceRecompute - Force the live range of ParentVNI in
RegIdx
to b
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SplitKit.cpp
373
VNInfo *SplitEditor::defValue(unsigned
RegIdx
,
379
LiveInterval *LI = &LIS.getInterval(Edit->get(
RegIdx
));
386
Values.insert(std::make_pair(std::make_pair(
RegIdx
, ParentVNI->id),
389
// This was the first time (
RegIdx
, ParentVNI) was mapped.
409
void SplitEditor::forceRecompute(unsigned
RegIdx
, const VNInfo *ParentVNI) {
411
ValueForcePair &VFP = Values[std::make_pair(
RegIdx
, ParentVNI->id)];
424
LiveInterval *LI = &LIS.getInterval(Edit->get(
RegIdx
));
430
VNInfo *SplitEditor::defFromParent(unsigned
RegIdx
,
437
LiveInterval *LI = &LIS.getInterval(Edit->get(
RegIdx
));
440
// so always begin
RegIdx
0 early and all others late
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...]
LiveVariables.cpp
85
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned
RegIdx
) {
86
assert(TargetRegisterInfo::isVirtualRegister(
RegIdx
) &&
88
VirtRegInfo.grow(
RegIdx
);
89
return VirtRegInfo[
RegIdx
];
/external/llvm/lib/Target/R600/InstPrinter/
AMDGPUInstPrinter.cpp
104
unsigned
RegIdx
= MRI.getEncodingValue(reg) & ((1 << 8) - 1);
106
O << Type <<
RegIdx
;
110
O << Type << '[' <<
RegIdx
<< ':' << (
RegIdx
+ NumRegs - 1) << ']';
/external/llvm/include/llvm/CodeGen/
LiveVariables.h
270
VarInfo &getVarInfo(unsigned
RegIdx
);
/external/llvm/lib/Target/Mips/
MipsSEISelDAGToDAG.h
33
unsigned getMSACtrlReg(const SDValue
RegIdx
) const;
MipsSEISelDAGToDAG.cpp
70
unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue
RegIdx
) const {
71
switch (cast<ConstantSDNode>(
RegIdx
)->getZExtValue()) {
730
SDValue
RegIdx
= Node->getOperand(2);
732
getMSACtrlReg(
RegIdx
), MVT::i32);
762
SDValue
RegIdx
= Node->getOperand(2);
765
getMSACtrlReg(
RegIdx
), Value);
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
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Completed in 118 milliseconds