| /art/compiler/dex/quick/arm/ |
| arm_lir.h | 113 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
114 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
115 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
116 r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3,
118 rARM_SUSPEND = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4
[all...] |
| codegen_arm.h | 34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src
[all...] |
| target_arm.cc | 29 static constexpr RegStorage core_regs_arr[] =
33 static constexpr RegStorage core_regs_arr[] =
37 static constexpr RegStorage sp_regs_arr[] =
42 static constexpr RegStorage dp_regs_arr[] =
46 static constexpr RegStorage reserved_regs_arr[] =
48 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r12};
50 static constexpr RegStorage reserved_regs_arr[] =
52 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r4, rs_r12};
54 static constexpr RegStorage sp_temps_arr[] =
57 static constexpr RegStorage dp_temps_arr[]
[all...] |
| utility_arm.cc | 73 DCHECK(RegStorage::IsSingle(r_dest));
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
238 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
371 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type)
[all...] |
| /art/compiler/dex/quick/mips/ |
| mips_lir.h | 119 #define rMIPS_LR RegStorage::kInvalidRegVal
120 #define rMIPS_PC RegStorage::kInvalidRegVal
146 rZERO = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
147 rAT = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
148 rV0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
149 rV1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3
[all...] |
| codegen_mips.h | 34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src
[all...] |
| target_mips.cc | 29 static constexpr RegStorage core_regs_arr[] =
33 static constexpr RegStorage sp_regs_arr[] =
36 static constexpr RegStorage dp_regs_arr[] =
38 static constexpr RegStorage reserved_regs_arr[] =
40 static constexpr RegStorage core_temps_arr[] =
43 static constexpr RegStorage sp_temps_arr[] =
46 static constexpr RegStorage dp_temps_arr[] =
49 static constexpr ArrayRef<const RegStorage> empty_pool;
50 static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr);
51 static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr)
[all...] |
| utility_mips.cc | 25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
37 RegStorage t_opnd = r_src;
79 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
82 RegStorage r_dest_save = r_dest;
116 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
131 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
151 RegStorage r_scratch = AllocTemp();
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2)
[all...] |
| call_mips.cc | 85 RegStorage r_end = AllocTemp();
104 RegStorage r_base = AllocTemp();
112 RegStorage r_key = AllocTemp();
118 RegStorage r_disp = AllocTemp();
162 RegStorage r_key;
197 RegStorage r_base = AllocTemp();
201 RegStorage r_disp = AllocTemp();
246 RegStorage r_tgt = LoadHelper(kQuickHandleFillArrayData);
264 RegStorage reset_reg = AllocTempRef();
275 void MipsMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg)
[all...] |
| int_mips.cc | 48 RegStorage t0 = AllocTemp();
49 RegStorage t1 = AllocTemp();
65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
118 RegStorage t_reg = AllocTemp();
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
135 RegStorage t_reg = AllocTemp();
152 RegStorage t_reg = AllocTemp();
163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src)
[all...] |
| /art/compiler/dex/ |
| reg_storage_eq.h | 24 // Define == and != operators for RegStorage. These are based on exact equality of the reg storage,
28 inline bool operator==(const RegStorage& lhs, const RegStorage& rhs) {
32 inline bool operator!=(const RegStorage& lhs, const RegStorage& rhs) {
|
| reg_storage.h | 68 * one view will affect the other views. The RegStorage class does not concern itself
70 * Distinct RegStorage elements should be created for each view of a physical register
75 class RegStorage {
107 constexpr RegStorage(RegStorageKind rs_kind, int reg)
113 constexpr RegStorage(RegStorageKind rs_kind, int low_reg, int high_reg)
123 constexpr explicit RegStorage(uint16_t val) : reg_(val) {}
124 RegStorage() : reg_(kInvalid) {}
133 bool ExactlyEquals(const RegStorage& rhs) const {
137 bool NotExactlyEquals(const RegStorage& rhs) const {
232 // Create a stand-alone RegStorage from the low reg of a pair
[all...] |
| reg_location.h | 52 RegStorage reg; // Encoded physical registers.
|
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 118 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
119 r0q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0,
121 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
122 r1q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 1,
124 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2
[all...] |
| codegen_x86.h | 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0;
39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref);
54 RegStorage Get(int in_position);
57 std::map<int, RegStorage> mapping_;
71 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale
[all...] |
| target_x86.cc | 30 static constexpr RegStorage core_regs_arr_32[] = {
33 static constexpr RegStorage core_regs_arr_64[] = {
37 static constexpr RegStorage core_regs_arr_64q[] = {
41 static constexpr RegStorage sp_regs_arr_32[] = {
44 static constexpr RegStorage sp_regs_arr_64[] = {
48 static constexpr RegStorage dp_regs_arr_32[] = {
51 static constexpr RegStorage dp_regs_arr_64[] = {
55 static constexpr RegStorage xp_regs_arr_32[] = {
58 static constexpr RegStorage xp_regs_arr_64[] = {
62 static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}
[all...] |
| utility_x86.cc | 29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
81 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
82 RegStorage r_dest_save = r_dest;
120 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
133 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
195 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
229 // TODO: Similar to Arm's reg < 8 check. Perhaps add attribute checks to RegStorage?
251 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type)
[all...] |
| call_x86.cc | 83 RegStorage start_of_method_reg;
100 RegStorage keyReg;
113 RegStorage disp_reg = AllocTemp();
152 RegStorage array_ptr = TargetReg(kArg0, kRef);
153 RegStorage payload = TargetPtrReg(kArg1);
154 RegStorage method_start = TargetPtrReg(kArg2);
188 void X86Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) {
191 RegStorage reg_card_base = AllocTempRef();
192 RegStorage reg_card_no = AllocTempRef()
[all...] |
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0;
40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref);
53 RegStorage Get(int in_position);
56 std::map<int, RegStorage> mapping_;
74 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale
[all...] |
| arm64_lir.h | 132 rw##nr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | nr, \
133 rx##nr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | nr, \
134 rf##nr = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | nr, \
135 rd##nr = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | nr,
139 rxzr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0x3f
[all...] |
| target_arm64.cc | 29 static constexpr RegStorage core_regs_arr[] =
35 static constexpr RegStorage core64_regs_arr[] =
41 static constexpr RegStorage sp_regs_arr[] =
46 static constexpr RegStorage dp_regs_arr[] =
53 static constexpr RegStorage reserved_regs_arr[] =
55 static constexpr RegStorage reserved64_regs_arr[] =
57 static constexpr RegStorage core_temps_arr[] =
61 static constexpr RegStorage core64_temps_arr[] =
65 static constexpr RegStorage sp_temps_arr[] =
69 static constexpr RegStorage dp_temps_arr[]
[all...] |
| utility_arm64.cc | 110 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) {
134 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) {
392 LIR* Arm64Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
456 LIR* Arm64Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
550 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) {
634 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
669 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2)
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 341 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll);
375 RegStorage GetReg() { return reg_; }
376 void SetReg(RegStorage reg) { reg_ = reg; }
389 RegStorage Partner() { return partner_; }
390 void SetPartner(RegStorage partner) { partner_ = partner; }
424 RegStorage reg_;
429 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register.
444 const ArrayRef<const RegStorage>& core_regs,
445 const ArrayRef<const RegStorage>& core64_regs,
446 const ArrayRef<const RegStorage>& sp_regs
[all...] |
| ralloc_util.cc | 41 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask)
59 const ArrayRef<const RegStorage>& core_regs,
60 const ArrayRef<const RegStorage>& core64_regs,
61 const ArrayRef<const RegStorage>& sp_regs,
62 const ArrayRef<const RegStorage>& dp_regs,
63 const ArrayRef<const RegStorage>& reserved_regs,
64 const ArrayRef<const RegStorage>& reserved64_regs,
65 const ArrayRef<const RegStorage>& core_temps,
66 const ArrayRef<const RegStorage>& core64_temps,
67 const ArrayRef<const RegStorage>& sp_temps
[all...] |
| local_optimizations.cc | 70 void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src) {
93 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id));
94 RegStorage dest_reg, src_reg;
103 switch (reg_id & RegStorage::kShapeTypeMask) {
104 case RegStorage::k32BitSolo | RegStorage::kCoreRegister:
105 dest_reg = RegStorage::Solo32(lir->operands[0]);
106 src_reg = RegStorage::Solo32(reg_id);
108 case RegStorage::k64BitSolo | RegStorage::kCoreRegister
[all...] |
