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Searched
refs:SrcIdx
(Results
1 - 9
of
9
) sorted by null
/external/llvm/lib/CodeGen/
RegisterCoalescer.h
42
///
SrcIdx
- The sub-register index of the old SrcReg in the new coalesced
44
unsigned
SrcIdx
;
63
: TRI(tri), DstReg(0), SrcReg(0), DstIdx(0),
SrcIdx
(0),
70
: TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0),
SrcIdx
(0),
113
unsigned getSrcIdx() const { return
SrcIdx
; }
PeepholeOptimizer.cpp
185
bool getNextSourceImpl(unsigned &
SrcIdx
, unsigned &SrcSubReg);
187
bool getNextSourceFromCopy(unsigned &
SrcIdx
, unsigned &SrcSubReg);
189
bool getNextSourceFromBitcast(unsigned &
SrcIdx
, unsigned &SrcSubReg);
192
bool getNextSourceFromRegSequence(unsigned &
SrcIdx
, unsigned &SrcSubReg);
195
bool getNextSourceFromInsertSubreg(unsigned &
SrcIdx
, unsigned &SrcSubReg);
198
bool getNextSourceFromExtractSubreg(unsigned &
SrcIdx
, unsigned &SrcSubReg);
201
bool getNextSourceFromSubregToReg(unsigned &
SrcIdx
, unsigned &SrcSubReg);
231
/// \p
SrcIdx
gives the index of the next source in the returned
235
const MachineInstr *getNextSource(unsigned &
SrcIdx
, unsigned &SrcSubReg);
462
unsigned
SrcIdx
, DefIdx
[
all
...]
TwoAddressInstructionPass.cpp
129
unsigned
SrcIdx
, unsigned DstIdx,
[
all
...]
RegisterCoalescer.cpp
253
SrcIdx
= DstIdx = 0;
300
SrcIdx
, DstIdx);
305
SrcIdx
= DstSub;
322
if (DstIdx && !
SrcIdx
) {
324
std::swap(
SrcIdx
, DstIdx);
343
std::swap(
SrcIdx
, DstIdx);
367
assert(!DstIdx && !
SrcIdx
&& "Inconsistent CoalescerPair state.");
381
return TRI.composeSubRegIndices(
SrcIdx
, SrcSub) ==
735
unsigned
SrcIdx
= CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
770
// If both
SrcIdx
and DstIdx are set, correct rematerialization would wide
[
all
...]
/external/llvm/lib/Target/R600/
R600InstrInfo.h
108
int getSelIdx(unsigned Opcode, unsigned
SrcIdx
) const;
283
/// \param
SrcIdx
The register source to set the flag on (e.g src0, src1, src2)
287
MachineOperand &getFlagOp(MachineInstr *MI, unsigned
SrcIdx
= 0,
R600InstrInfo.cpp
272
int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned
SrcIdx
) const {
288
if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)
SrcIdx
) {
334
int
SrcIdx
= getOperandIdx(MI->getOpcode(), OpTable[j][0]);
335
if (
SrcIdx
< 0)
337
MachineOperand &MO = MI->getOperand(
SrcIdx
);
338
unsigned Reg = MI->getOperand(
SrcIdx
).getReg();
[
all
...]
R600ISelLowering.cpp
[
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...]
/external/llvm/lib/Transforms/InstCombine/
InstCombineVectorOps.cpp
262
int
SrcIdx
= SVI->getMaskValue(Elt->getZExtValue());
267
if (
SrcIdx
< 0)
269
if (
SrcIdx
< (int)LHSWidth)
272
SrcIdx
-= LHSWidth;
278
SrcIdx
, false));
[
all
...]
/external/llvm/lib/Analysis/
DependenceAnalysis.cpp
[
all
...]
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