| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_inlines.h | 63 case TYPE_F64:
82 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
94 return (ty >= TYPE_F16 && ty <= TYPE_F64);
|
| nv50_ir_emit_nv50.cpp | 561 case TYPE_F64: // fall through
836 if (i->dType == TYPE_F64) {
1118 case TYPE_F64:
1120 case TYPE_F64: code[1] = 0xc4404000; break;
1133 case TYPE_F64: code[1] = 0x8c404000; break;
1142 case TYPE_F64: code[1] = 0x84404000; break;
1151 case TYPE_F64: code[1] = 0xc0404000; break;
1165 case TYPE_F64: code[1] = 0x88404000; break;
1181 case TYPE_F64: code[1] = 0x80404000; break;
[all...] |
| nv50_ir.cpp | 351 reg.type = TYPE_F64;
398 case TYPE_F64:
414 case TYPE_F64: return reg.data.u64 & (1ULL << 63);
449 case TYPE_F64:
|
| nv50_ir_target_nv50.cpp | 375 if (ty == TYPE_F64 && chipset < 0xa0)
505 if (i->dType == TYPE_F64) {
|
| nv50_ir_peephole.cpp | 351 case TYPE_F64:
409 case TYPE_F64: res.data.f64 = a->data.f64 * b->data.f64; break;
421 case TYPE_F64: res.data.f64 = a->data.f64 / b->data.f64; break;
431 case TYPE_F64: res.data.f64 = a->data.f64 + b->data.f64; break;
441 case TYPE_F64: res.data.f64 = pow(a->data.f64, b->data.f64); break;
449 case TYPE_F64: res.data.f64 = MAX2(a->data.f64, b->data.f64); break;
459 case TYPE_F64: res.data.f64 = MIN2(a->data.f64, b->data.f64); break;
[all...] |
| nv50_ir_print.cpp | 384 case TYPE_F64: PRINT("%f", reg.data.f64); break;
|
| nv50_ir_from_sm4.cpp | 318 return TYPE_F64;
339 return TYPE_F64;
[all...] |
| nv50_ir.h | 163 TYPE_F64,
|
| nv50_ir_lowering_nv50.cpp | 166 if (i->dType == TYPE_F64) {
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_inlines.h | 63 case TYPE_F64:
82 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
94 return (ty >= TYPE_F16 && ty <= TYPE_F64);
|
| nv50_ir_emit_nv50.cpp | 561 case TYPE_F64: // fall through
836 if (i->dType == TYPE_F64) {
1118 case TYPE_F64:
1120 case TYPE_F64: code[1] = 0xc4404000; break;
1133 case TYPE_F64: code[1] = 0x8c404000; break;
1142 case TYPE_F64: code[1] = 0x84404000; break;
1151 case TYPE_F64: code[1] = 0xc0404000; break;
1165 case TYPE_F64: code[1] = 0x88404000; break;
1181 case TYPE_F64: code[1] = 0x80404000; break;
[all...] |
| nv50_ir.cpp | 351 reg.type = TYPE_F64;
398 case TYPE_F64:
414 case TYPE_F64: return reg.data.u64 & (1ULL << 63);
449 case TYPE_F64:
|
| nv50_ir_target_nv50.cpp | 375 if (ty == TYPE_F64 && chipset < 0xa0)
505 if (i->dType == TYPE_F64) {
|
| nv50_ir_peephole.cpp | 351 case TYPE_F64:
409 case TYPE_F64: res.data.f64 = a->data.f64 * b->data.f64; break;
421 case TYPE_F64: res.data.f64 = a->data.f64 / b->data.f64; break;
431 case TYPE_F64: res.data.f64 = a->data.f64 + b->data.f64; break;
441 case TYPE_F64: res.data.f64 = pow(a->data.f64, b->data.f64); break;
449 case TYPE_F64: res.data.f64 = MAX2(a->data.f64, b->data.f64); break;
459 case TYPE_F64: res.data.f64 = MIN2(a->data.f64, b->data.f64); break;
[all...] |
| nv50_ir_print.cpp | 384 case TYPE_F64: PRINT("%f", reg.data.f64); break;
|
| nv50_ir_from_sm4.cpp | 318 return TYPE_F64;
339 return TYPE_F64;
[all...] |
| nv50_ir.h | 163 TYPE_F64,
|
| nv50_ir_lowering_nv50.cpp | 166 if (i->dType == TYPE_F64) {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 543 if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
635 if (i->dType == TYPE_F64) {
|
| nv50_ir_lowering_nvc0.cpp | 111 if (i->dType == TYPE_F64)
488 if (i->dType == TYPE_F64) {
[all...] |
| nv50_ir_emit_nvc0.cpp | 874 if (i->sType == TYPE_F64)
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 543 if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
635 if (i->dType == TYPE_F64) {
|
| nv50_ir_lowering_nvc0.cpp | 111 if (i->dType == TYPE_F64)
488 if (i->dType == TYPE_F64) {
[all...] |
| nv50_ir_emit_nvc0.cpp | 874 if (i->sType == TYPE_F64)
[all...] |
