/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 128 MIB.addReg(AM.Base.Reg) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 103 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 105 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 108 .addReg(HEXAGON_RESERVED_REG_1) 109 .addImm(0).addReg(HEXAGON_RESERVED_REG_2); 112 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 114 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 117 .addReg(HEXAGON_RESERVED_REG_1) 119 .addReg(HEXAGON_RESERVED_REG_2); 123 HEXAGON_RESERVED_REG_2).addReg(SrcReg) [all...] |
HexagonSplitTFRCondSets.cpp | 116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 136 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 141 addReg(MI->getOperand(1).getReg()). 146 addReg(MI->getOperand(1).getReg()). 162 addReg(MI->getOperand(1).getReg()). 167 addReg(MI->getOperand(1).getReg()) [all...] |
HexagonRegisterInfo.cpp | 180 dstReg).addReg(FrameReg).addReg(dstReg); 184 dstReg).addReg(FrameReg).addImm(Offset); 209 resReg).addReg(FrameReg).addReg(resReg); 213 resReg).addReg(FrameReg).addImm(Offset); 240 TII.get(Hexagon::ADD_rr), ResReg).addReg(FrameReg). 241 addReg(ResReg); 247 TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg). 260 dstReg).addReg(FrameReg).addReg(dstReg) [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 61 .addReg(MI->getOperand(0).getReg()) 62 .addReg(MI->getOperand(1).getReg()) 63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) 74 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D) [all...] |
/external/llvm/lib/Target/R600/ |
SILowerControlFlow.cpp | 142 .addReg(AMDGPU::EXEC); 161 .addReg(AMDGPU::EXEC); 170 .addReg(AMDGPU::VGPR0) 171 .addReg(AMDGPU::VGPR0) 172 .addReg(AMDGPU::VGPR0) 173 .addReg(AMDGPU::VGPR0); 186 .addReg(Vcc); 189 .addReg(AMDGPU::EXEC) 190 .addReg(Reg); 205 .addReg(Src); // Saved EXE [all...] |
/external/llvm/lib/Target/ARM/ |
ARMAsmPrinter.cpp | [all...] |
Thumb2RegisterInfo.cpp | 50 .addReg(DestReg, getDefRegState(true), SubIdx) 51 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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ARMFrameLowering.cpp | 319 .addImm((unsigned)ARMCC::AL).addReg(0) 321 .addReg(ARM::R4, RegState::Implicit) 331 .addImm((unsigned)ARMCC::AL).addReg(0) 332 .addReg(ARM::R12, RegState::Kill) 333 .addReg(ARM::R4, RegState::Implicit) 340 .addReg(ARM::SP, RegState::Define) 341 .addReg(ARM::R4, RegState::Kill) 523 .addReg(ARM::SP, RegState::Kill) 533 .addReg(ARM::SP, RegState::Kill)); 536 .addReg(ARM::R4, RegState::Kill [all...] |
Thumb2InstrInfo.cpp | 122 .addReg(SrcReg, getKillRegState(KillSrc))); 145 .addReg(SrcReg, getKillRegState(isKill)) 205 MIB.addReg(DestReg, RegState::ImplicitDefine); 219 .addReg(BaseReg, RegState::Kill) 220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 242 .addReg(DestReg) 244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 251 .addReg(BaseReg, RegState::Kill) 252 .addReg(DestReg, RegState::Kill [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmInstrumentation.cpp | 164 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP) 165 .addReg(X86::ESP).addImm(-16)); 166 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg)); 180 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); 181 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); 182 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX)); 194 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); 195 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) 196 .addReg(X86::ECX).addImm(3)) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 71 .addReg(FrameReg) 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 78 .addReg(FrameReg) 84 .addReg(FrameReg) 107 .addReg(FrameReg) 108 .addReg(ScratchOffset, RegState::Kill) 113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 114 .addReg(FrameReg) 115 .addReg(ScratchOffset, RegState::Kill) 120 .addReg(FrameReg [all...] |
/external/llvm/lib/Target/Mips/ |
MipsLongBranch.cpp | 234 MIB.addReg(MO.getReg()); 294 .addReg(Mips::SP).addImm(-8); 295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 296 .addReg(Mips::SP).addImm(0); 319 .addReg(Mips::AT) 326 .addReg(Mips::RA).addReg(Mips::AT); 328 .addReg(Mips::SP).addImm(0); 332 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) 334 .addReg(Mips::SP).addImm(8)) [all...] |
MipsSEInstrInfo.cpp | 111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 132 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 133 .addReg(DestReg, RegState::ImplicitDefine); 173 MIB.addReg(DestReg, RegState::Define); 176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 179 MIB.addReg(ZeroReg); 221 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill) [all...] |
/external/llvm/include/llvm/MC/ |
MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) {
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/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 304 .addReg(SrcReg) 308 .addReg(SrcReg, RegState::Kill) 313 .addReg(SrcReg) 317 .addReg(SrcReg, RegState::Kill) 322 .addReg(SrcReg) 326 .addReg(SrcReg, RegState::Kill) 330 .addReg(DstReg, RegState::Kill) 629 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 635 .addReg(FPReg) 637 .addReg(SPReg) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc)); 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) 62 .addReg(0) // PREDICATE_BIT 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 72 .addReg(SrcReg, getKillRegState(KillSrc)) 74 .addReg(0); // PREDICATE_BIT 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); 85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT 271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0) [all...] |
R600ISelLowering.cpp | 69 .addReg(AMDGPU::PRED_SEL_OFF); 80 .addReg(AMDGPU::PRED_SEL_OFF); 92 .addReg(AMDGPU::PRED_SEL_OFF); 103 .addReg(ConstantReg); 131 .addReg(AMDGPU::ALU_LITERAL_X) 132 .addReg(AMDGPU::PRED_SEL_OFF) 136 .addReg(ShiftValue) 137 .addReg(AMDGPU::PRED_SEL_OFF); 140 .addReg(NewAddr) 173 .addReg(t0, RegState::Implicit [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXFrameLowering.cpp | 53 NVPTX::VRFrame).addReg(LocalReg); 62 NVPTX::VRFrame).addReg(LocalReg);
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NVPTXInstrInfo.cpp | 47 .addReg(SrcReg, getKillRegState(KillSrc)); 50 .addReg(SrcReg, getKillRegState(KillSrc)); 53 .addReg(SrcReg, getKillRegState(KillSrc)); 56 .addReg(SrcReg, getKillRegState(KillSrc)); 59 .addReg(SrcReg, getKillRegState(KillSrc)); 62 .addReg(SrcReg, getKillRegState(KillSrc)); 264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
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/external/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.cpp | 125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 126 .addReg(FramePtr); 141 .addReg(SP::G1).addImm(LOX10(Offset)); 143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 144 .addReg(FramePtr); 183 .addReg(FramePtr).addImm(0).addReg(SrcEvenReg); 195 .addReg(FramePtr).addImm(0);
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc)); 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) 62 .addReg(0) // PREDICATE_BIT 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 72 .addReg(SrcReg, getKillRegState(KillSrc)) 74 .addReg(0); // PREDICATE_BIT 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); 85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT 271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0) [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 71 .addReg(MSP430::SPW); 99 .addReg(MSP430::SPW).addImm(NumBytes); 157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); 162 .addReg(MSP430::SPW).addImm(CSSize); 171 .addReg(MSP430::SPW).addImm(NumBytes); 200 .addReg(Reg, RegState::Kill); 249 .addReg(MSP430::SPW).addImm(Amount); 258 .addReg(MSP430::SPW).addImm(Amount); 276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt) [all...] |