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  /bionic/libc/upstream-netbsd/lib/libc/isc/
ev_timers.c 189 struct timespec due,
197 "evSetTimer(ctx %p, func %p, uap %p, due %ld.%09ld, inter %ld.%09ld)\n",
199 (long)due.tv_sec, due.tv_nsec,
206 if (due.tv_nsec >= BILLION)
212 if (due.tv_sec < 0 || due.tv_nsec < 0 || due.tv_nsec >= BILLION)
219 /* due={0,0} is a magic cookie meaning "now." */
220 if (due.tv_sec == (time_t)0 && due.tv_nsec == 0L
    [all...]
  /external/llvm/test/MC/Mips/
mips-register-names-invalid.s 4 # $32 used to trigger an assertion instead of the usual error message due to
  /external/bison/
GNUmakefile 89 .DEFAULT_GOAL := abort-due-to-no-makefile
101 ifeq ($(.DEFAULT_GOAL),abort-due-to-no-makefile)
102 $(MAKECMDGOALS): abort-due-to-no-makefile
105 abort-due-to-no-makefile:
  /external/chromium_org/ui/file_manager/file_manager/foreground/js/ui/
file_manager_dialog_base.js 52 * dialog failed to show due to an existing dialog.
65 * dialog failed to show due to an existing dialog.
84 * dialog failed to show due to an existing dialog.
93 * dialog failed to show due to an existing dialog.
103 * dialog failed to show due to an existing dialog.
  /external/oprofile/events/mips/rm9000/
events 27 event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
29 event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
30 event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
32 event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non-blocking loads - stall start of exception
  /external/oprofile/events/mips/25K/
events 43 event:0x15 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch
44 event:0x16 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access
73 event:0x23 counters:0,1 um:zero minimum:500 name:REPLAYS_LOAD_DEP_DISPATCH : replays due to load-dependent speculative dispatch
74 event:0x24 counters:0,1 um:zero minimum:500 name:REPLAYS_WBB_FULL : replays due to WBB full
75 event:0x25 counters:0,1 um:zero minimum:500 name:FSB_FULL_REPLAYS : replays due to FSB full
  /external/oprofile/events/mips/74K/
events 21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
29 event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
30 event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full
36 event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy
37 event:0x13 counters:0,2 um:zero minimum:500 name:ALU_BUBBLE_CYCLES : 19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write
45 event:0x1b counters:0,2 um:zero minimum:500 name:LOAD_STORE_BLOCKED_CYCLES : 27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO ful
    [all...]
  /external/oprofile/events/i386/nehalem/
unit_masks 22 0x0F any All loads delayed due to store blocks
25 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB
29 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB
160 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
175 0x04 m_evict Counts the number of modified lines evicted from the L1 data cache due to replacement
176 0x08 m_snoop_evict Counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention
189 0x04 cycles_stalled Cycle counts for which an instruction fetch stalls due to a L1I cache miss, ITLB miss or ITLB fault
203 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
205 0x01 lcp Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX
206 0x02 mru Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypas
    [all...]
  /external/oprofile/events/mips/rm7000/
events 28 event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
30 event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
34 event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non-blocking loads - stall start of exception
  /external/antlr/antlr-3.4/runtime/Perl5/lib/ANTLR/
Runtime.pm 77 This may be due to name conflicts in the interface, or competition for
78 system or program resources, or due to internal limitations of Perl
  /external/chromium_org/remoting/webapp/browser_test/
invalid_pin_browser_test.js 11 * 3. Verify that there is connection error due to invalid access code.
  /cts/
CtsBuild.mk 30 # File indicating which tests should be blacklisted due to problems.
33 # File indicating which tests should be blacklisted due to unsupported abi.
  /external/llvm/test/MC/ARM/
arm-memory-instructions.s 31 @ label operands currently assert the show-encoding asm comment helper due
  /external/oprofile/events/mips/sb1/
events 28 event:0x25 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_IMISS :issue conflict due to imiss using LS0
29 event:0x26 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_DFILL :issue conflict due to dfill using LS0/1
48 event:0xd counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to replacement
  /external/antlr/antlr-3.4/runtime/Ruby/test/functional/parser/
backtracking.rb 44 * The LL(*) analysis algorithm fails to deal with this due to
  /external/chromium_org/ppapi/native_client/tests/breakpad_crash_test/
nacl.scons 52 # DISABLED due to flakiness (http://crbug.com/247114).
74 # DISABLED due to flakiness (http://crbug.com/332331)
  /external/chromium_org/v8/test/webkit/fast/js/
stack-overflow-arrity-catch.js 41 // now cause a stack overflow exception due to arrity processing
72 // now cause a stack overflow exception due to arrity processing
  /external/oprofile/events/mips/1004K/
events 60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
67 event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
69 event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions
72 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
92 event:0x3a counters:0 um:zero minimum:500 name:EVICTION_COUNT : 58-0 Cache lines written back due to cache replacement or non-coherent cache operation
134 event:0x424 counters:1 um:zero minimum:500 name:INTERVENTION_MISS_STALLS : 36-1 Cache coherence intervention processing stall cycles due to an earlier miss
139 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
169 event:0x43a counters:1 um:zero minimum:500 name:WRITEBACK_COUNT : 58-1 Cache lines written back due to cache replacement or any cache operation (non-coherent, self, or external coherent)
  /external/antlr/antlr-3.4/runtime/Perl5/lib/ANTLR/Runtime/
BitSet.pm 343 This may be due to name conflicts in the interface, or competition for
344 system or program resources, or due to internal limitations of Perl
  /external/chromium_org/chrome/renderer/resources/extensions/
tag_watcher.js 36 // reporting error due to lack of permission).
  /external/chromium_org/remoting/webapp/
host.js 42 * app (a difference of 1 is tolerated due to the different update mechanisms)
  /external/chromium_org/v8/test/webkit/
dfg-proto-access-inline-osr-exit.js 25 "Tests what happens when we OSR exit on an inlined prototype access due to a change in the prototype chain."
  /external/eigen/lapack/
dladiv.f 39 *> The algorithm is due to Robert L. Smith and can be found
sladiv.f 39 *> The algorithm is due to Robert L. Smith and can be found
  /external/oprofile/events/mips/20K/
events 14 event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch

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