| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 82 v16i32 = 36, // 16 x i32 enumerator in enum:llvm::MVT::SimpleValueType
227 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32);
291 case v16i32: return i32;
324 case v16i32:
424 case v16i32:
539 if (NumElements == 16) return MVT::v16i32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 231 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
232 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
235 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
260 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
261 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
406 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 154 case MVT::v16i32: return "v16i32";
222 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 52 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
87 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
[all...] |
| AMDGPUISelLowering.cpp | 152 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
198 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 453 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost },
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 95 case MVT::v16i32: return "MVT::v16i32";
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
