| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 59 const TargetRegisterInfo *TRI;
126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
132 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
241 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
286 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287 << " in " << PrintReg(LR.PhysReg, TRI));
291 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
366 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
372 assert(TRI->isSuperRegister(PhysReg, Alias) &&
376 MO.getParent()->addRegisterKilled(Alias, TRI, true)
[all...] |
| TailDuplication.cpp | 64 const TargetRegisterInfo *TRI;
139 TRI = MF.getTarget().getRegisterInfo();
146 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
801 BitVector RegsLiveAtExit(TRI->getNumRegs());
[all...] |
| TargetInstrInfo.cpp | 43 const TargetRegisterInfo *TRI,
50 return TRI->getPointerRegClass(MF, RegClass);
57 return TRI->getRegClass(RegClass);
319 const TargetRegisterInfo &TRI) const {
321 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
501 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
504 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
506 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
659 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
660 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
[all...] |
| InlineSpiller.cpp | 70 const TargetRegisterInfo &TRI;
155 TRI(*mf.getTarget().getRegisterInfo()),
745 MRI.getRegClass(SVI.SpillReg), &TRI);
[all...] |
| MachineInstr.cpp | 69 const TargetRegisterInfo &TRI) {
72 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
78 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 Reg = TRI.getSubReg(Reg, getSubReg());
268 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr;
272 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| MachineLICM.cpp | 67 const TargetRegisterInfo *TRI;
114 // Tri-state: 0 - false, 1 - true, 2 - unknown
330 TRI = TM->getRegisterInfo();
345 unsigned NumRC = TRI->getNumRegClasses();
349 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
350 E = TRI->regclass_end(); I != E; ++I)
351 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
452 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
472 for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
500 unsigned NumRegs = TRI->getNumRegs()
[all...] |
| MachineVerifier.cpp | 69 const TargetRegisterInfo *TRI;
95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
296 TRI = TM->getRegisterInfo();
461 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
683 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
693 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
[all...] |
| TwoAddressInstructionPass.cpp | 73 const TargetRegisterInfo *TRI;
293 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
494 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
499 return TRI->regsOverlap(RegA, RegB);
547 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
548 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
614 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
638 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 286 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
353 for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) {
484 unsigned NbReg, const TargetRegisterInfo *TRI,
490 DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 47 const TargetRegisterInfo *TRI;
357 const TargetRegisterInfo *TRI, unsigned &D0,
360 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
361 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
362 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
367 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
368 D3 = TRI->getSubReg(Reg, ARM::dsub_6)
[all...] |
| ARMAsmPrinter.cpp | 139 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
140 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
232 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
235 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
238 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
264 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
265 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
267 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
320 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
321 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q'
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | 232 const AMDGPURegisterInfo *TRI =
315 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
327 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
|
| R600ControlFlowFinalizer.cpp | 220 const R600RegisterInfo *TRI;
293 DstMI = TRI->getMatchingSuperReg(Reg,
294 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
302 SrcMI = TRI->getMatchingSuperReg(Reg,
303 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
473 TII (nullptr), TRI(nullptr),
481 TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/ |
| intel_tris.c | 554 #define TRI( a, b, c ) \
864 #define RENDER_TRI( v0, v1, v2 ) TRI( V(v0), V(v1), V(v2) )
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 388 #define TRI( a, b, c ) r200_triangle( rmesa, a, b, c )
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 510 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 705 /// TRI::getReservedRegs() when possible.
709 "Use TRI::getReservedRegs().");
764 const TargetRegisterInfo &TRI,
[all...] |
| ScheduleDAG.h | 556 const TargetRegisterInfo *TRI; // Target processor register info
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
270 unsigned RegNo = TRI->getEncodingValue(I->first);
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_tris.c | 554 #define TRI( a, b, c ) \
864 #define RENDER_TRI( v0, v1, v2 ) TRI( V(v0), V(v1), V(v2) )
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 388 #define TRI( a, b, c ) r200_triangle( rmesa, a, b, c )
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 510 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
|
| /external/eigen/blas/testing/ |
| cblat2.f | [all...] |
