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  /external/llvm/test/CodeGen/AArch64/
arm64-vecCmpBr.ll 1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
203 attributes #0 = { nounwind ssp "target-cpu"="cyclone" }
204 attributes #1 = { "target-cpu"="cyclone" }
arm64-fast-isel-br.ll 1 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
arm64-memcpy-inline.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
arm64-rounding.ll 1 ; RUN: llc -O3 < %s -mcpu=cyclone | FileCheck %s
arm64-stur.ll 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
arm64-vshuffle.ll 1 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
arm64-abi-varargs.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
arm64-arith-saturating.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
arm64-fcmp-opt.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
arm64-fp128.ll 1 ; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
arm64-patchpoint.ll 1 ; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone | FileCheck %s
arm64-promote-const.ll 3 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s
6 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s
arm64-abi.ll 1 ; RUN: llc < %s -debug -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
arm64-atomic-128.ll 1 ; RUN: llc < %s -march=arm64 -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
  /external/clang/test/CodeGen/
arm64_vecCmpBr.c 1 // RUN: %clang_cc1 -O3 -triple arm64-apple-ios7 -target-feature +neon -S -ffreestanding %s -o - -target-cpu cyclone | FileCheck %s
aarch64-neon-scalar-x-indexed-elem.c 2 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \
  /external/clang/test/Preprocessor/
aarch64-target-features.c 55 // RUN: %clang -target aarch64-none-linux-gnu -mcpu=cyclone -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FEATURE %s
  /external/llvm/lib/Target/AArch64/
AArch64StorePairSuppress.cpp 101 /// cyclone, these require a vector shuffle before storing a pair.
AArch64Subtarget.cpp 122 // LNT run (at least on Cyclone) showed reasonably significant gains for
AArch64ISelLowering.h 221 // FIXME: True for Cyclone, but not necessary others.
  /external/llvm/test/Transforms/LoopStrengthReduce/AArch64/
req-regs.ll 1 ; RUN: llc -mcpu=cyclone -debug-only=loop-reduce < %s 2>&1 | FileCheck %s
lsr-memset.ll 1 ; RUN: llc < %s -O3 -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid | FileCheck %s
  /external/llvm/test/Transforms/LoopVectorize/AArch64/
gather-cost.ll 1 ; RUN: opt -loop-vectorize -mtriple=arm64-apple-ios -S -mcpu=cyclone < %s | FileCheck %s
  /external/llvm/lib/Target/ARM/
ARM.td 76 // Cyclone has preferred instructions for zeroing VFP registers, which can
414 // Cyclone is very similar to swift
415 def : ProcessorModel<"cyclone", SwiftModel,
  /external/clang/test/Driver/
aarch64-cpus.c 14 // ARM64-DARWIN: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cyclone"

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