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    Searched full:do_div (Results 51 - 64 of 64) sorted by null

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/prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/
div64.h	26 #define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; }) macro 30 #define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; }) macro
/external/strace/
vsprintf.c	27 #define do_div(n, d) ({ __typeof(num) t = n % d; n /= d; t; }) macro 160 buf = put_dec_full9(buf, do_div(n, 1000*1000*1000)); 323 tmp[i++] = (digits[do_div(num,base)]);
/external/chromium_org/third_party/freetype/src/truetype/
ttinterp.c	[all...]
/external/freetype/src/truetype/
ttinterp.c	[all...]
/external/pdfium/core/src/fxge/fx_freetype/fxft2.5.01/src/truetype/
ttinterp.c	[all...]
/prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.8/lib/
libmips64el-unknown-linux-android-sim.a	37 ?pcb_read_target_syscall_mapscb_target_to_host_syscallcb_host_to_target_errnocb_target_to_host_opencb_store_target_endiancb_host_to_target_statsim_cb_printfsim_cb_eprintfcb_is_stdincb_is_stdoutcb_is_stderrdefault_callbacksimulator_sysrootcb_syscallcb_init_open_mapcb_init_errno_mapcb_init_syscall_mapversionsemantic_illegaldelayslot32nullify_next_insn32loadstore_eanot_word_valueunpredictablecheck_mf_cyclescheck_mt_hilocheck_mf_hilocheck_mult_hilocheck_div_hilocheck_u64do_addiudo_addudo_anddo_daddiudo_daddudo_ddivdo_ddivudo_divdo_divudo_dmultxdo_dmultdo_dmultudo_drordo_dslldo_dsllvdo_dsrado_dsravdo_dsrldo_dsrlvdo_dsubudo_loaddo_load_leftdo_load_rightdo_mfhido_mflodo_multdo_multudo_nordo_ordo_orido_rordo_storedo_store_leftdo_store_rightdo_slldo_sllvdo_sltdo_sltido_sltiudo_sltudo_srado_sravdo_srldo_srlvdo_subudo_xordo_xoristr_FMTstr_TFstr_NDstr_CONDcheck_fmt_pcheck_fpudelayslot16basepcdo_savestr_MFHIstr_SATstr_UNSdo_vr_mul_opdo_ph_opdo_w_opdo_qb_opdo_qb_shiftdo_ph_shiftdo_w_shlldo_w_shrado_qb_muleudo_ph_mulqdo_ph_muleqdo_qb_dot_productdo_ph_dot_productdo_w_dot_productdo_ph_maqdo_qb_cmpudo_qb_cmpgudo_ph_cmpudo_w_extrdo_h_extrdo_extpdo_shilodo_u_ph_opdo_uh_qb_opdo_qb_cmpgdudo_w_ph_dot_productdo_w_mulqdo_precr_srado_qb_shrado_ph_shrldo_qh_ph_opdo_qh_w_opdo_x_w_ph_dot_productdo_qx_w_ph_dot_productitableitable_processor_namesitable_option_namesitable_flag_namessemantic_RSVD_SPECIALsemantic_SYSCALL_SPECIALsemantic_BREAK_SPECIALsemantic_TGE_SPECIALsemantic_TGEU_SPECIALsemantic_TLT_SPECIALsemantic_TLTU_SPECIALsemantic_TEQ_SPECIALsemantic_TNE_SPECIALsemantic_SLLV_SPECIALsemantic_SRLV_SPECIALsemantic_SRAV_SPECIALsemantic_MOVZ_SPECIALsemantic_MOVN_SPECIALsemantic_DSLLV_SPECIALsemantic_DSRLV_SPECIALsemantic_DSRAV_SPECIALsemantic_ADD_SPECIALsemantic_ADDU_SPECIALsemantic_SUB_SPECIALsemantic_SUBU_SPECIALsemantic_AND_SPECIALsemantic_OR_SPECIALsemantic_XOR_SPECIALsemantic_NOR_SPECIALsemantic_SLT_SPECIALsemantic_SLTU_SPECIALsemantic_DADD_SPECIALsemantic_DADDU_SPECIALsemantic_DSUB_SPECIALsemantic_DSUBU_SPECIALsemantic_MULT_SPECIALsemantic_MULTU_SPECIALsemantic_DIV_SPECIALsemantic_DIVU_SPECIALsemantic_DMULT_SPECIALsemantic_DMULTU_SPECIALsemantic_DDIV_SPECIALsemantic_DDIVU_SPECIALsemantic_MOVtf_SPECIALsemantic_JALR_SPECIALsemantic_JR_SPECIALsemantic_MTHI_SPECIALsemantic_MTLO_SPECIALsemantic_SLLa_SPECIALsemantic_SRL_SPECIALsemantic_SRA_SPECIALsemantic_DSLL_SPECIALsemantic_DSRL_SPECIALsemantic_DSRA_SPECIALsemantic_DSLL32_SPECIALsemantic_DSRL32_SPECIALsemantic_DSRA32_SPECIALsemantic_MFHI_SPECIALsemantic_MFLO_SPECIALsemantic_SYNC_SPECIALsemantic_BLTZ_REGIMMsemantic_BGEZ_REGIMMsemantic_BLTZL_REGIMMsemantic_BGEZL_REGIMMsemantic_TGEI_REGIMMsemantic_TGEIU_REGIMMsemantic_TLTI_REGIMMsemantic_TLTIU_REGIMMsemantic_TEQI_REGIMMsemantic_TNEI_REGIMMsemantic_BLTZAL_REGIMMsemantic_BGEZAL_REGIMMsemantic_BLTZALL_REGIMMsemantic_BGEZALL_REGIMMsemantic_J_NORMALsemantic_JAL_NORMALsemantic_BEQ_NORMALsemantic_BNE_NORMALsemantic_BLEZ_NORMALsemantic_BGTZ_NORMALsemantic_ADDI_NORMALsemantic_ADDIU_NORMALsemantic_SLTI_NORMALsemantic_SLTIU_NORMALsemantic_ANDI_NORMALsemantic_ORI_NORMALsemantic_XORI_NORMALsemantic_LUI_NORMALsemantic_COPz_NORMALsemantic_MFC0_COP0semantic_DMFC0_COP0semantic_MTC0_COP0semantic_DMTC0_COP0semantic_BC0F_COP0semantic_BC0T_COP0semantic_BC0FL_COP0semantic_BC0TL_COP0semantic_TLBR_COP0semantic_TLBWI_COP0semantic_TLBWR_COP0semantic_TLBP_COP0semantic_RFE_COP0semantic_ERET_COP0semantic_MFC1b_COP1semantic_DMFC1b_COP1semantic_CFC1b_COP1semantic_MTC1b_COP1semantic_DMTC1b_COP1semantic_CTC1b_COP1semantic_BC1b_COP1Ssemantic_ADD_fmt_COP1semantic_SUB_fmt_COP1semantic_MUL_fmt_COP1semantic_DIV_fmt_COP1semantic_MOVZ_fmt_COP1semantic_MOVN_fmt_COP1semantic_C_cond_fmtb_COP1semantic_MOVtf_fmt_COP1semantic_SQRT_fmt_COP1semantic_ABS_fmt_COP1semantic_MOV_fmt_COP1semantic_NEG_fmt_COP1semantic_ROUND_L_fmt_COP1semantic_TRUNC_L_fmt_COP1semantic_CEIL_L_fmt_COP1semantic_FLOOR_L_fmt_COP1semantic_ROUND_W_fmt_COP1semantic_TRUNC_W_COP1semantic_CEIL_W_COP1semantic_FLOOR_W_fmt_COP1semantic_RECIP_fmt_COP1semantic_RSQRT_fmt_COP1semantic_CVT_S_fmt_COP1semantic_CVT_D_fmt_COP1semantic_CVT_W_fmt_COP1semantic_CVT_L_fmt_COP1semantic_MADD_fmt_COP1Xsemantic_MSUB_fmt_COP1Xsemantic_NMADD_fmt_COP1Xsemantic_NMSUB_fmt_COP1Xsemantic_SWXC1_COP1Xsemantic_SDXC1_COP1Xsemantic_PREFX_COP1Xsemantic_LWXC1_COP1Xsemantic_LDXC1_COP1Xsemantic_BEQL_NORMALsemantic_BNEL_NORMALsemantic_BLEZL_NORMALsemantic_BGTZL_NORMALsemantic_DADDI_NORMALsemantic_DADDIU_NORMALsemantic_LDL_NORMALsemantic_LDR_NORMALsemantic_LB_NORMALsemantic_LH_NORMALsemantic_LWL_NORMALsemantic_LW_NORMALsemantic_LBU_NORMALsemantic_LHU_NORMALsemantic_LWR_NORMALsemantic_LWU_NORMALsemantic_SB_NORMALsemantic_SH_NORMALsemantic_SWL_NORMALsemantic_SW_NORMALsemantic_SDL_NORMALsemantic_SDR_NORMALsemantic_SWR_NORMALsemantic_CACHE_NORMALsemantic_LWCz_NORMALsemantic_LL_NORMALsemantic_LWC1_COP1semantic_PREF_NORMALsemantic_LDCz_NORMALsemantic_LLD_NORMALsemantic_LDC1b_COP1semantic_LD_NORMALsemantic_SWCz_NORMALsemantic_SC_NORMALsemantic_SWC1_COP1semantic_SDCz_NORMALsemantic_SCD_NORMALsemantic_SDC1b_COP1semantic_SD_NORMALidecode_issueengine_runsim_engine_runsim_addr_range_hit_psim_addr_range_addsim_addr_range_deletesim_config_defaultsim_configcurrent_target_byte_ordercurrent_host_byte_ordercurrent_stdiocurrent_alignmentcurrent_floating_pointprint_sim_configsim_core_installsim_core_signalsim_core_attachsim_core_detachsim_core_read_buffersim_core_write_buffersim_core_set_xorsim_core_xor_read_buffersim_core_xor_write_buffersim_core_trans_addrsim_core_read_aligned_16sim_core_read_unaligned_16sim_core_write_aligned_16sim_core_write_unaligned_16sim_core_read_aligned_8sim_core_read_unaligned_8sim_core_write_aligned_8sim_core_write_unaligned_8sim_core_read_misaligned_7sim_core_write_misaligned_7sim_core_read_misaligned_6sim_core_write_misaligned_6sim_core_read_misaligned_5sim_core_write_misaligned_5sim_core_read_aligned_4sim_core_read_unaligned_4sim_core_write_aligned_4sim_core_write_unaligned_4sim_core_read_misaligned_3sim_core_write_misaligned_3sim_core_read_aligned_2sim_core_read_unaligned_2sim_core_write_aligned_2sim_core_write_unaligned_2sim_core_read_aligned_1sim_core_write_aligned_1sim_events_installsim_events_timesim_events_elapsed_timesim_events_remain_timesim_events_schedule_vtracefsim_events_schedule_tracefsim_events_schedulesim_events_schedule_after_signalsim_events_watch_clocksim_events_watch_simsim_events_watch_coresim_events_deschedulesim_events_ticksim_events_ticknsim_events_slipsim_events_processsim_events_preprocesssim_fpu_32tosim_fpu_232tosim_fpu_64tosim_fpu_to32sim_fpu_to232sim_fpu_to64sim_fpu_fractiontosim_fpu_tofractionsim_fpu_round_32sim_fpu_round_64sim_fpu_addsim_fpu_subsim_fpu_mulsim_fpu_divsim_fpu_maxsim_fpu_minsim_fpu_negsim_fpu_abssim_fpu_invsim_fpu_onesim_fpu_sqrtsim_fpu_i32tosim_fpu_u32tosim_fpu_i64tosim_fpu_u64tosim_fpu_to32isim_fpu_to32usim_fpu_to64isim_fpu_to64usim_fpu_2dsim_fpu_d2sim_fpu_is_nansim_fpu_is_qnansim_fpu_is_snansim_fpu_is_zerosim_fpu_is_infinitysim_fpu_is_numbersim_fpu_is_denormsim_fpu_signsim_fpu_expsim_fpu_fractionsim_fpu_guardsim_fpu_issim_fpu_cmpsim_fpu_ltsim_fpu_is_ltsim_fpu_is_gtsim_fpu_lesim_fpu_is_lesim_fpu_is_gesim_fpu_eqsim_fpu_is_eqsim_fpu_nesim_fpu_is_nesim_fpu_gesim_fpu_gtsim_fpu_printn_fpusim_fpu_print_fpusim_fpu_print_statussim_fpu_max64sim_fpu_max32sim_fpu_twosim_fpu_qnansim_fpu_zerosim_io_initsim_io_shutdownsim_io_unlinksim_io_timesim_io_systemsim_io_renamesim_io_writesim_io_readsim_io_opensim_io_lseeksim_io_isattysim_io_get_errnosim_io_closesim_io_printfsim_io_vprintfsim_io_eprintfsim_io_evprintfsim_io_errorsim_io_read_stdinsim_io_flush_stderrsim_io_write_stderrsim_io_flush_stdoutsim_io_write_stdoutsim_io_poll_quitsim_io_poll_readsim_io_statsim_io_fstatsim_infosim_load_filesim_memopt_installsim_module_initsim_post_argv_initsim_module_resumesim_module_suspendsim_module_uninstallsim_module_installsim_pre_argv_initsim_module_infosim_module_add_init_fnsim_module_add_resume_fnsim_module_add_suspend_fnsim_module_add_uninstall_fnsim_module_add_info_fnsim_add_option_tablestandard_installsim_parse_argssim_print_helpsim_args_commandset_profile_option_masksim_profile_set_optionsim_profile_print_barprofile_installsim_signal_to_hostsim_signal_to_targettrace_installtrace_input0trace_input_word1trace_input_word2trace_input_word3trace_input_word4trace_input_bool1trace_input_addr1trace_input_fp1trace_input_fp2trace_input_fp3trace_input_fpu1trace_input_fpu2trace_input_fpu3trace_vprintftrace_printftrace_one_insntrace_result_word1_string1trace_result_string1trace_result_fpu1trace_result_fp2trace_result_fp1trace_result_addr1trace_result_bool1trace_result_word4trace_result_word2trace_result0trace_result_word1trace_prefixtrace_genericdebug_printfzallocsim_state_allocsim_state_freesim_cpu_lookupsim_cpu_msg_prefixsim_io_eprintf_cpusim_add_commassim_analyze_programsim_elapsed_time_getsim_elapsed_time_sincesim_do_commandfmap_to_straccess_to_strtransfer_to_strcurrent_statesim_watchpoint_installvalue_fprstore_fprtest_fcsrvalue_fcrstore_fcrupdate_fcsrfp_cmpfp_absfp_negfp_addfp_subfp_mulfp_divfp_recipfp_sqrtfp_rsqrtfp_maddfp_msubfp_nmaddfp_nmsubfp_add_rfp_mul_rfp_recip1fp_recip2fp_rsqrt1fp_rsqrt2convertps_lowerps_upperpack_psconvert_pssim_closetracefhsim_writesim_readsim_store_registersim_fetch_registersim_create_inferiorsim_do_commandsim_openinterrupt_eventsim_monitorcop_lwcop_ldcop_swcop_sdpr_addrunpredictable_actiondotracepr_uword64mips_cpu_exception_triggersignal_exceptionmips_core_signaldecode_coprocinterrupt_pendingmips_cpu_exception_suspendmips_cpu_exception_resumemdmx_cpr_opmdmx_cc_opmdmx_pick_opmdmx_acc_opmdmx_rac_opmdmx_waclmdmx_wachmdmx_round_opmdmx_shuffleDSPHI_REGNUMDSPLO_REGNUMaddress_translationprefetchload_memorystore_memoryifetch32ifetch16sync_operationcache_oppending_ticksim_loadsim_engine_get_run_statesim_engine_set_run_statesim_engine_haltsim_engine_restartsim_engine_vabortsim_engine_abortsim_engine_last_cpu_nrsim_engine_next_cpu_nrsim_engine_nr_cpussim_engine_installsim_stopsim_resumesim_stop_reasoncallback.o/ 1386722519 1249825000 100640 15520 `     [all...]
/prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/
libmips64el-unknown-linux-android-sim.a	37 ??cb_read_target_syscall_mapscb_target_to_host_syscallcb_host_to_target_errnocb_target_to_host_opencb_store_target_endiancb_host_to_target_statsim_cb_printfsim_cb_eprintfcb_is_stdincb_is_stdoutcb_is_stderrdefault_callbackcb_get_stringsimulator_sysrootcb_syscallcb_init_open_mapcb_init_errno_mapcb_init_syscall_mapversionsemantic_illegaldelayslot32nullify_next_insn32loadstore_eanot_word_valueunpredictablecheck_mf_cyclescheck_mt_hilocheck_mf_hilocheck_mult_hilocheck_div_hilocheck_u64do_addiudo_addudo_anddo_daddiudo_daddudo_ddivdo_ddivudo_divdo_divudo_dmultxdo_dmultdo_dmultudo_drordo_dslldo_dsllvdo_dsrado_dsravdo_dsrldo_dsrlvdo_dsubudo_loaddo_load_leftdo_load_rightdo_mfhido_mflodo_multdo_multudo_nordo_ordo_orido_rordo_storedo_store_leftdo_store_rightdo_slldo_sllvdo_sltdo_sltido_sltiudo_sltudo_srado_sravdo_srldo_srlvdo_subudo_xordo_xoristr_FMTstr_TFstr_NDstr_CONDcheck_fmt_pcheck_fpudelayslot16basepcdo_savestr_MFHIstr_SATstr_UNSdo_vr_mul_opdo_ph_opdo_w_opdo_qb_opdo_qb_shiftdo_ph_shiftdo_w_shlldo_w_shrado_qb_muleudo_ph_mulqdo_ph_muleqdo_qb_dot_productdo_ph_dot_productdo_w_dot_productdo_ph_maqdo_qb_cmpudo_qb_cmpgudo_ph_cmpudo_w_extrdo_h_extrdo_extpdo_shilodo_u_ph_opdo_uh_qb_opdo_qb_cmpgdudo_w_ph_dot_productdo_w_mulqdo_precr_srado_qb_shrado_ph_shrldo_qh_ph_opdo_qh_w_opdo_x_w_ph_dot_productdo_qx_w_ph_dot_productitableitable_processor_namesitable_option_namesitable_flag_namessemantic_RSVD_SPECIALsemantic_SYSCALL_SPECIALsemantic_BREAK_SPECIALsemantic_TGE_SPECIALsemantic_TGEU_SPECIALsemantic_TLT_SPECIALsemantic_TLTU_SPECIALsemantic_TEQ_SPECIALsemantic_TNE_SPECIALsemantic_SLLV_SPECIALsemantic_SRLV_SPECIALsemantic_SRAV_SPECIALsemantic_MOVZ_SPECIALsemantic_MOVN_SPECIALsemantic_DSLLV_SPECIALsemantic_DSRLV_SPECIALsemantic_DSRAV_SPECIALsemantic_ADD_SPECIALsemantic_ADDU_SPECIALsemantic_SUB_SPECIALsemantic_SUBU_SPECIALsemantic_AND_SPECIALsemantic_OR_SPECIALsemantic_XOR_SPECIALsemantic_NOR_SPECIALsemantic_SLT_SPECIALsemantic_SLTU_SPECIALsemantic_DADD_SPECIALsemantic_DADDU_SPECIALsemantic_DSUB_SPECIALsemantic_DSUBU_SPECIALsemantic_MULT_SPECIALsemantic_MULTU_SPECIALsemantic_DIV_SPECIALsemantic_DIVU_SPECIALsemantic_DMULT_SPECIALsemantic_DMULTU_SPECIALsemantic_DDIV_SPECIALsemantic_DDIVU_SPECIALsemantic_MOVtf_SPECIALsemantic_JALR_SPECIALsemantic_JR_SPECIALsemantic_MTHI_SPECIALsemantic_MTLO_SPECIALsemantic_SLLa_SPECIALsemantic_SRL_SPECIALsemantic_SRA_SPECIALsemantic_DSLL_SPECIALsemantic_DSRL_SPECIALsemantic_DSRA_SPECIALsemantic_DSLL32_SPECIALsemantic_DSRL32_SPECIALsemantic_DSRA32_SPECIALsemantic_MFHI_SPECIALsemantic_MFLO_SPECIALsemantic_SYNC_SPECIALsemantic_BLTZ_REGIMMsemantic_BGEZ_REGIMMsemantic_BLTZL_REGIMMsemantic_BGEZL_REGIMMsemantic_TGEI_REGIMMsemantic_TGEIU_REGIMMsemantic_TLTI_REGIMMsemantic_TLTIU_REGIMMsemantic_TEQI_REGIMMsemantic_TNEI_REGIMMsemantic_BLTZAL_REGIMMsemantic_BGEZAL_REGIMMsemantic_BLTZALL_REGIMMsemantic_BGEZALL_REGIMMsemantic_J_NORMALsemantic_JAL_NORMALsemantic_BEQ_NORMALsemantic_BNE_NORMALsemantic_BLEZ_NORMALsemantic_BGTZ_NORMALsemantic_ADDI_NORMALsemantic_ADDIU_NORMALsemantic_SLTI_NORMALsemantic_SLTIU_NORMALsemantic_ANDI_NORMALsemantic_ORI_NORMALsemantic_XORI_NORMALsemantic_LUI_NORMALsemantic_COPz_NORMALsemantic_MFC0_COP0semantic_DMFC0_COP0semantic_MTC0_COP0semantic_DMTC0_COP0semantic_BC0F_COP0semantic_BC0T_COP0semantic_BC0FL_COP0semantic_BC0TL_COP0semantic_TLBR_COP0semantic_TLBWI_COP0semantic_TLBWR_COP0semantic_TLBP_COP0semantic_RFE_COP0semantic_ERET_COP0semantic_MFC1b_COP1semantic_DMFC1b_COP1semantic_CFC1b_COP1semantic_MTC1b_COP1semantic_DMTC1b_COP1semantic_CTC1b_COP1semantic_BC1b_COP1Ssemantic_ADD_fmt_COP1semantic_SUB_fmt_COP1semantic_MUL_fmt_COP1semantic_DIV_fmt_COP1semantic_MOVZ_fmt_COP1semantic_MOVN_fmt_COP1semantic_C_cond_fmtb_COP1semantic_MOVtf_fmt_COP1semantic_SQRT_fmt_COP1semantic_ABS_fmt_COP1semantic_MOV_fmt_COP1semantic_NEG_fmt_COP1semantic_ROUND_L_fmt_COP1semantic_TRUNC_L_fmt_COP1semantic_CEIL_L_fmt_COP1semantic_FLOOR_L_fmt_COP1semantic_ROUND_W_fmt_COP1semantic_TRUNC_W_COP1semantic_CEIL_W_COP1semantic_FLOOR_W_fmt_COP1semantic_RECIP_fmt_COP1semantic_RSQRT_fmt_COP1semantic_CVT_S_fmt_COP1semantic_CVT_D_fmt_COP1semantic_CVT_W_fmt_COP1semantic_CVT_L_fmt_COP1semantic_MADD_fmt_COP1Xsemantic_MSUB_fmt_COP1Xsemantic_NMADD_fmt_COP1Xsemantic_NMSUB_fmt_COP1Xsemantic_SWXC1_COP1Xsemantic_SDXC1_COP1Xsemantic_PREFX_COP1Xsemantic_LWXC1_COP1Xsemantic_LDXC1_COP1Xsemantic_BEQL_NORMALsemantic_BNEL_NORMALsemantic_BLEZL_NORMALsemantic_BGTZL_NORMALsemantic_DADDI_NORMALsemantic_DADDIU_NORMALsemantic_LDL_NORMALsemantic_LDR_NORMALsemantic_LB_NORMALsemantic_LH_NORMALsemantic_LWL_NORMALsemantic_LW_NORMALsemantic_LBU_NORMALsemantic_LHU_NORMALsemantic_LWR_NORMALsemantic_LWU_NORMALsemantic_SB_NORMALsemantic_SH_NORMALsemantic_SWL_NORMALsemantic_SW_NORMALsemantic_SDL_NORMALsemantic_SDR_NORMALsemantic_SWR_NORMALsemantic_CACHE_NORMALsemantic_LWCz_NORMALsemantic_LL_NORMALsemantic_LWC1_COP1semantic_PREF_NORMALsemantic_LDCz_NORMALsemantic_LLD_NORMALsemantic_LDC1b_COP1semantic_LD_NORMALsemantic_SWCz_NORMALsemantic_SC_NORMALsemantic_SWC1_COP1semantic_SDCz_NORMALsemantic_SCD_NORMALsemantic_SDC1b_COP1semantic_SD_NORMALidecode_issueengine_runsim_engine_runsim_addr_range_hit_psim_addr_range_addsim_addr_range_deletesim_do_commandsim_config_defaultsim_configcurrent_target_byte_ordercurrent_host_byte_ordercurrent_stdiocurrent_alignmentcurrent_floating_pointprint_sim_configsim_core_installsim_core_signalsim_core_attachsim_core_detachsim_core_read_buffersim_core_write_buffersim_core_set_xorsim_core_xor_read_buffersim_core_xor_write_buffersim_core_trans_addrsim_core_read_aligned_16sim_core_read_unaligned_16sim_core_write_aligned_16sim_core_write_unaligned_16sim_core_read_aligned_8sim_core_read_unaligned_8sim_core_write_aligned_8sim_core_write_unaligned_8sim_core_read_misaligned_7sim_core_write_misaligned_7sim_core_read_misaligned_6sim_core_write_misaligned_6sim_core_read_misaligned_5sim_core_write_misaligned_5sim_core_read_aligned_4sim_core_read_unaligned_4sim_core_write_aligned_4sim_core_write_unaligned_4sim_core_read_misaligned_3sim_core_write_misaligned_3sim_core_read_aligned_2sim_core_read_unaligned_2sim_core_write_aligned_2sim_core_write_unaligned_2sim_core_read_aligned_1sim_core_write_aligned_1sim_events_installsim_events_timesim_events_elapsed_timesim_events_remain_timesim_events_schedule_vtracefsim_events_schedule_tracefsim_events_schedulesim_events_schedule_after_signalsim_events_watch_clocksim_events_watch_simsim_events_watch_coresim_events_deschedulesim_events_ticksim_events_ticknsim_events_slipsim_events_processsim_events_preprocesssim_fpu_32tosim_fpu_232tosim_fpu_64tosim_fpu_to32sim_fpu_to232sim_fpu_to64sim_fpu_fractiontosim_fpu_tofractionsim_fpu_round_32sim_fpu_round_64sim_fpu_addsim_fpu_subsim_fpu_mulsim_fpu_divsim_fpu_maxsim_fpu_minsim_fpu_negsim_fpu_abssim_fpu_invsim_fpu_onesim_fpu_sqrtsim_fpu_i32tosim_fpu_u32tosim_fpu_i64tosim_fpu_u64tosim_fpu_to32isim_fpu_to32usim_fpu_to64isim_fpu_to64usim_fpu_2dsim_fpu_d2sim_fpu_is_nansim_fpu_is_qnansim_fpu_is_snansim_fpu_is_zerosim_fpu_is_infinitysim_fpu_is_numbersim_fpu_is_denormsim_fpu_signsim_fpu_expsim_fpu_fractionsim_fpu_guardsim_fpu_issim_fpu_cmpsim_fpu_ltsim_fpu_is_ltsim_fpu_is_gtsim_fpu_lesim_fpu_is_lesim_fpu_is_gesim_fpu_eqsim_fpu_is_eqsim_fpu_nesim_fpu_is_nesim_fpu_gesim_fpu_gtsim_fpu_printn_fpusim_fpu_print_fpusim_fpu_print_statussim_fpu_max64sim_fpu_max32sim_fpu_twosim_fpu_qnansim_fpu_zerosim_io_initsim_io_shutdownsim_io_unlinksim_io_timesim_io_systemsim_io_renamesim_io_writesim_io_readsim_io_opensim_io_lseeksim_io_isattysim_io_get_errnosim_io_closesim_io_printfsim_io_vprintfsim_io_eprintfsim_io_evprintfsim_io_errorsim_io_read_stdinsim_io_flush_stderrsim_io_write_stderrsim_io_flush_stdoutsim_io_write_stdoutsim_io_poll_quitsim_io_poll_readsim_io_statsim_io_fstatsim_infosim_load_filesim_memopt_installsim_module_initsim_post_argv_initsim_module_resumesim_module_suspendsim_module_uninstallsim_module_installsim_pre_argv_initsim_module_infosim_module_add_init_fnsim_module_add_resume_fnsim_module_add_suspend_fnsim_module_add_uninstall_fnsim_module_add_info_fnsim_add_option_tablestandard_installsim_parse_argssim_print_helpsim_complete_commandsim_args_commandset_profile_option_masksim_profile_set_optionsim_profile_print_barprofile_installsim_signal_to_hostsim_signal_to_gdb_signaltrace_installsave_datatrace_input0trace_input_word1trace_input_word2trace_input_word3trace_input_word4trace_input_bool1trace_input_addr1trace_input_fp1trace_input_fp2trace_input_fp3trace_input_fpu1trace_input_fpu2trace_input_fpu3trace_vprintftrace_printftrace_one_insntrace_result_word1_string1trace_result_string1trace_result_fpu1trace_result_fp2trace_result_fp1trace_result_addr1trace_result_bool1trace_result_word4trace_result_word2trace_result0trace_result_word1trace_prefixtrace_genericdebug_printfzallocsim_state_allocsim_state_freesim_cpu_lookupsim_cpu_msg_prefixsim_io_eprintf_cpusim_add_commassim_analyze_programsim_elapsed_time_getsim_elapsed_time_sincesim_do_commandfmap_to_straccess_to_strtransfer_to_strcurrent_statesim_watchpoint_installvalue_fprstore_fprtest_fcsrvalue_fcrstore_fcrupdate_fcsrfp_cmpfp_absfp_negfp_addfp_subfp_mulfp_divfp_recipfp_sqrtfp_rsqrtfp_maddfp_msubfp_nmaddfp_nmsubfp_add_rfp_mul_rfp_recip1fp_recip2fp_rsqrt1fp_rsqrt2convertps_lowerps_upperpack_psconvert_pssim_closetracefhsim_writesim_openinterrupt_eventsim_readsim_store_registersim_fetch_registersim_create_inferiorsim_monitorcop_lwcop_ldcop_swcop_sdpr_addrunpredictable_actiondotracepr_uword64mips_cpu_exception_triggersignal_exceptionmips_core_signaldecode_coprocinterrupt_pendingmips_cpu_exception_suspendmips_cpu_exception_resumemdmx_cpr_opmdmx_cc_opmdmx_pick_opmdmx_acc_opmdmx_rac_opmdmx_waclmdmx_wachmdmx_round_opmdmx_shuffleDSPHI_REGNUMDSPLO_REGNUMaddress_translationprefetchload_memorystore_memoryifetch32ifetch16sync_operationcache_oppending_ticksim_loadsim_engine_get_run_statesim_engine_set_run_statesim_engine_haltsim_engine_restartsim_engine_vabortsim_engine_abortsim_engine_last_cpu_nrsim_engine_next_cpu_nrsim_engine_nr_cpussim_engine_installsim_stopsim_resumesim_stop_reasoncallback.o/ 1405502596 1249825000 100640 15520 `     [all...]
/prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.8/lib/
libmipsel-unknown-linux-android-sim.a	10 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