| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 25 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 20 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 29 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 21 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/main/none/tests/mips64/ |
| fpu_arithmetic.c | 109 TRIOPf("msub.s");
114 TRIOPd("msub.d");
|
| arithmetic_instruction.c | 11 MADD, MADDU, MSUB, MSUBU,
220 case MSUB:
224 TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
|
| macro_fpu.h | 31 "rsqrt.s", "rsqrt.d", "msub.s", "msub.d",
|
| /external/llvm/test/CodeGen/Mips/ |
| fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
73 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
88 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
163 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
172 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
240 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
256 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
332 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
350 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 46 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips32.s | 39 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5-wrong-error.s | 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| 3rf_4rf_q.ll | 117 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
122 declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
142 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
147 declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 24 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 19 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/aac/libFDK/include/mips/ |
| cplx_mul.h | 113 "msub %[a_Im], %[b_Im];\n"
142 "msub %[a_Im], %[b_Im];\n"
|
| /external/llvm/test/CodeGen/AArch64/ |
| dp-3source.ll | 23 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
31 ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/mips/dspr2/ |
| vp9_itrans8_dspr2.c | 61 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
101 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
121 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
256 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
296 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
316 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
[all...] |
| /external/libvpx/libvpx/vp9/common/mips/dspr2/ |
| vp9_itrans8_dspr2.c | 61 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
101 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
121 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
256 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
296 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
316 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 66 # CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
67 # CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11]
129 # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
130 # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
188 msub.s $f2, $f4, $f6, $f8
189 msub.d $f2, $f4, $f6, $f8
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/mips/dspr2/ |
| vp9_itrans8_dspr2.c | 61 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
101 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
121 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
256 "msub $ac0, %[Temp1], %[cospi_8_64] \n\t"
296 "msub $ac0, %[Temp1], %[cospi_4_64] \n\t"
316 "msub $ac0, %[Temp1], %[cospi_20_64] \n\t"
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 104 msub $s7,$k1
105 msub.d $f10,$f1,$f31,$f18
106 msub.s $f12,$f19,$f10,$f16
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid-xfail.s | 195 msub $ac2,$sp,$14
196 msub.d $f10,$f1,$f31,$f18
197 msub.ps $f12,$f14,$f29,$f17
|
| /external/chromium_org/chrome/browser/resources/chromeos/chromevox/common/ |
| math_util.js | 118 cvox.MathUtil.SCRIPT_LIST = ['MSUB', 'MSUP', 'MSUBSUP', 'MUNDER', 'MOVER',
125 * <msub> attach a subscript to a base.
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5-wrong-error.s | 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
