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  /external/llvm/test/MC/Mips/
mips-register-names-o32.s 4 # Second byte of addiu with $zero at rt contains the number of the source
8 addiu $zero, $zero, 0 # CHECK: encoding: [0x24,0x00,0x00,0x00]
9 addiu $at, $zero, 0 # CHECK: encoding: [0x24,0x01,0x00,0x00]
10 addiu $v0, $zero, 0 # CHECK: encoding: [0x24,0x02,0x00,0x00]
11 addiu $v1, $zero, 0 # CHECK: encoding: [0x24,0x03,0x00,0x00]
12 addiu $a0, $zero, 0 # CHECK: encoding: [0x24,0x04,0x00,0x00]
13 addiu $a1, $zero, 0 # CHECK: encoding: [0x24,0x05,0x00,0x00]
14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00]
15 addiu $a3, $zero, 0 # CHECK: encoding: [0x24,0x07,0x00,0x00
    [all...]
  /external/chromium_org/v8/test/mjsunit/regress/
regress-406.js 32 assertFalse(typeof(0) == "zero");
33 assertTrue(typeof(0) != "zero");
36 assertFalse(typeof(0) == "zero" && typeof(0) == "zero");
37 assertFalse(typeof(0) == "zero" && typeof(0) != "zero");
38 assertFalse(typeof(0) != "zero" && typeof(0) == "zero");
39 assertTrue(typeof(0) != "zero" && typeof(0) != "zero");
    [all...]
  /external/oprofile/events/mips/loongson2/
events 3 event:0x00 counters:0 um:zero minimum:10000 name:CPU_CLK_UNHALTED : Cycles outside of haltstate
4 event:0x01 counters:0 um:zero minimum:5000 name:BRANCH_INSTRUCTIONS : Branch instructions
5 event:0x02 counters:0 um:zero minimum:400 name:JUMP_INSTRUCTIONS : JR instructions
6 event:0x03 counters:0 um:zero minimum:500 name:JR31_INSTRUCTIONS : JR(rs=31) instructions
7 event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
8 event:0x05 counters:0 um:zero minimum:500 name:ALU1_ISSUED : ALU1 operation issued
9 event:0x06 counters:0 um:zero minimum:8000 name:MEM_ISSUED : Memory read/write issued
10 event:0x07 counters:0 um:zero minimum:300 name:FALU1_ISSUED : Float ALU1 operation issued
11 event:0x08 counters:0 um:zero minimum:200 name:BHT_BRANCH_INSTRUCTIONS : BHT prediction instructions
12 event:0x09 counters:0 um:zero minimum:200 name:MEM_READ : Read from primary memor
    [all...]
unit_masks 3 name:zero type:mandatory default:0x0
  /external/clang/test/Analysis/
ptr-arith.cpp 5 int zero; member in struct:X
11 zero = 1;
17 littleX.zero = 0;
20 return 5/littleX.zero; // no-warning
  /external/eigen/doc/snippets/
MatrixBase_setIdentity.cpp 1 Matrix4i m = Matrix4i::Zero();
  /external/oprofile/events/alpha/ev4/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/arm/mpcore/
unit_masks 3 name:zero type:mandatory default:0x00
  /external/oprofile/events/arm/xscale1/
unit_masks 3 name:zero type:mandatory default:0x00
  /external/oprofile/events/arm/xscale2/
unit_masks 3 name:zero type:mandatory default:0x00
  /external/oprofile/events/mips/r10000/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/mips/rm7000/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/mips/rm9000/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/mips/sb1/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/mips/vr5432/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/mips/vr5500/
unit_masks 4 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc/7450/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc/e300/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc/e500/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc/e500v2/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc64/970/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc64/pa6t/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc64/power4/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/ppc64/power5/
unit_masks 3 name:zero type:mandatory default:0x0
  /external/oprofile/events/rtc/
unit_masks 3 name:zero type:mandatory default:0x0

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