| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_program.h | 75 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
78 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK)
79 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK)
88 swizzle(int reg, int x, int y, int z, int w)
90 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
91 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
92 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1)
[all...] |
| /art/compiler/dex/quick/x86/ |
| fp_x86.cc | 63 RegStorage r_dest = rl_result.reg;
64 RegStorage r_src1 = rl_src1.reg;
65 RegStorage r_src2 = rl_src2.reg;
116 if (rl_result.reg == rl_src2.reg) {
117 rl_src2.reg = AllocTempDouble();
118 OpRegCopy(rl_src2.reg, rl_result.reg);
120 OpRegCopy(rl_result.reg, rl_src1.reg);
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 208 MOV(AL, 0, parts.count.reg,
209 reg_imm(parts.count.reg, ROR, GGL_DITHER_ORDER_SHIFT));
210 ADD(AL, 0, parts.count.reg, parts.count.reg,
212 MOV(AL, 0, parts.count.reg,
213 reg_imm(parts.count.reg, ROR, 32 - GGL_DITHER_ORDER_SHIFT));
265 AND(AL, 0, parts.dither.reg, parts.count.reg, imm(mask));
266 ADDR_ADD(AL, 0, parts.dither.reg, ctxtReg, parts.dither.reg);
1099 reg); local
1125 int i, r, reg; local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 96 imm.reg.type = type;
221 memset(®, 0, sizeof(reg));
222 reg.size = 4;
227 reg.file = file;
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1;
229 reg.data.id = -1;
244 reg.file = lval->reg.file;
245 reg.size = lval->reg.size
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 96 imm.reg.type = type;
221 memset(®, 0, sizeof(reg));
222 reg.size = 4;
227 reg.file = file;
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1;
229 reg.data.id = -1;
244 reg.file = lval->reg.file;
245 reg.size = lval->reg.size
[all...] |
| /external/qemu/distrib/ext4_utils/src/ |
| allocate.c | 101 static void region_list_remove(struct region_list *list, struct region *reg)
103 if (reg->prev)
104 reg->prev->next = reg->next;
106 if (reg->next)
107 reg->next->prev = reg->prev;
109 if (list->first == reg)
110 list->first = reg->next;
112 if (list->last == reg)
159 struct region *reg; local
266 struct region *reg = alloc->list.last->prev; local
392 struct region *reg; local
416 struct region *reg; local
447 struct region *reg = ext4_allocate_best_fit(len); local
464 struct region *reg = alloc->list.first; local
475 struct region *reg = alloc->list.first; local
486 struct region *reg = alloc->list.iter; local
499 struct region *reg = alloc->oob_list.iter; local
544 struct region *reg = alloc->list.iter; local
611 struct region *reg = list->iter; local
643 struct region *reg = ext4_allocate_best_fit(len); local
763 struct region *reg; local
[all...] |
| /external/libunwind/src/arm/ |
| Ginit.c | 42 uc_addr (unw_tdep_context_t *uc, int reg)
44 if (reg >= UNW_ARM_R0 && reg < UNW_ARM_R0 + 16)
45 return &uc->regs[reg - UNW_ARM_R0];
53 tdep_uc_addr (unw_tdep_context_t *uc, int reg)
55 return uc_addr (uc, reg);
121 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
127 if (unw_is_fpreg (reg))
130 Debug (16, "reg = %s\n", unw_regname (reg));
[all...] |
| /external/libunwind/src/hppa/ |
| Ginit.c | 44 uc_addr (ucontext_t *uc, int reg)
48 if ((unsigned) (reg - UNW_HPPA_GR) < 32)
49 addr = &uc->uc_mcontext.sc_gr[reg - UNW_HPPA_GR];
50 else if ((unsigned) (reg - UNW_HPPA_FR) < 32)
51 addr = &uc->uc_mcontext.sc_fr[reg - UNW_HPPA_FR];
60 _Uhppa_uc_addr (ucontext_t *uc, int reg)
62 return uc_addr (uc, reg);
134 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
140 if ((unsigned int) (reg - UNW_HPPA_FR) < 32)
143 addr = uc_addr (uc, reg);
[all...] |
| /external/libunwind/src/ia64/ |
| Gget_save_loc.c | 34 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc)
43 switch (reg)
57 loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_GR + 4))];
61 loc = c->loc[IA64_REG_NAT4 + (reg - (UNW_IA64_NAT + 4))];
62 reg_loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_NAT + 4))];
63 nat_bitnr = c->nat_bitnr[reg - (UNW_IA64_NAT + 4)];
74 loc = c->loc[IA64_REG_F16 + (reg - (UNW_IA64_FR + 16))];
92 case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
93 reg = rotate_gr (c, reg - UNW_IA64_GR)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/svgadump/ |
| svga_shader.h | 60 sh_reg_type( struct sh_reg reg )
62 return reg.type_lo | (reg.type_hi << 3);
73 struct sh_reg reg; member in struct:sh_def
80 struct sh_reg reg; member in struct:sh_defb
92 struct sh_reg reg; member in struct:sh_defi
142 sh_dstreg_type( struct sh_dstreg reg )
144 return reg.type_lo | (reg.type_hi << 3);
154 struct sh_dstreg reg; member in struct:sh_dcl
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| svga_shader.h | 60 sh_reg_type( struct sh_reg reg )
62 return reg.type_lo | (reg.type_hi << 3);
73 struct sh_reg reg; member in struct:sh_def
80 struct sh_reg reg; member in struct:sh_defb
92 struct sh_reg reg; member in struct:sh_defi
142 sh_dstreg_type( struct sh_dstreg reg )
144 return reg.type_lo | (reg.type_hi << 3);
154 struct sh_dstreg reg; member in struct:sh_dcl
[all...] |
| /external/valgrind/main/VEX/test/ |
| mmxtest.c | 85 #define mmx_m2r(op, mem, reg) \
90 __asm__ __volatile__ ("movq %%" #reg ", %0" \
93 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
94 __asm__ __volatile__ (#op " %0, %%" #reg \
97 __asm__ __volatile__ ("movq %%" #reg ", %0" \
100 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
103 #define mmx_r2m(op, reg, mem) \
106 __asm__ __volatile__ ("movq %%" #reg ", %0" \
109 fprintf(stderr, #op "_r2m(" #reg "=0x%016llx, ", mmx_trace.q); \
112 __asm__ __volatile__ (#op " %%" #reg ", %0"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_vertprog.h | 145 #define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE)
146 #define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE)
149 #define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE)
152 #define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE)
155 #define VSF_TMP(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, TMP, NONE
[all...] |
| /external/libunwind/src/aarch64/ |
| Ginit.c | 44 uc_addr (ucontext_t *uc, int reg)
46 if (reg >= UNW_AARCH64_X0 && reg <= UNW_AARCH64_V31)
47 return &uc->uc_mcontext.regs[reg];
55 tdep_uc_addr (ucontext_t *uc, int reg)
57 return uc_addr (uc, reg);
129 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
135 if (unw_is_fpreg (reg))
138 if (!(addr = uc_addr (uc, reg)))
144 Debug (12, "%s <- %lx\n", unw_regname (reg), *val)
[all...] |
| /external/libunwind/src/sh/ |
| Ginit.c | 43 uc_addr (ucontext_t *uc, int reg)
45 if (reg >= UNW_SH_R0 && reg <= UNW_SH_PR)
46 return &uc->uc_mcontext.gregs[reg];
54 tdep_uc_addr (ucontext_t *uc, int reg)
56 return uc_addr (uc, reg);
128 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
134 if (unw_is_fpreg (reg))
137 if (!(addr = uc_addr (uc, reg)))
143 Debug (12, "%s <- %x\n", unw_regname (reg), *val)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_vertprog.h | 145 #define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE)
146 #define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE)
149 #define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE)
152 #define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE)
155 #define VSF_TMP(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, TMP, NONE
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_clip_tri.c | 58 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
61 c->reg.fixed_planes = brw_vec4_grf(i, 0);
73 c->reg.vertex[j] = brw_vec4_grf(i, 0);
84 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
88 c->reg.t = brw_vec1_grf(i, 0);
89 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D);
90 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD);
91 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
92 c->reg.plane_equation = brw_vec4_grf(i, 4);
95 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 *
[all...] |
| /external/libunwind/src/mips/ |
| Gregs.c | 30 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp,
35 switch (reg)
69 loc = c->dwarf.loc[reg - UNW_MIPS_R0];
73 loc = c->dwarf.loc[reg];
85 Debug (1, "bad register number %u\n", reg);
98 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp,
101 Debug (1, "bad register number %u\n", reg);
|
| /external/libunwind/src/ppc32/ |
| Gregs.c | 31 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp,
36 switch (reg)
62 if ((((unsigned) (reg - UNW_PPC32_F0)) <= 31))
65 loc = c->dwarf.loc[reg];
74 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp,
79 if ((unsigned) (reg - UNW_PPC32_F0) < 32)
81 loc = c->dwarf.loc[reg];
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_clip_tri.c | 58 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
61 c->reg.fixed_planes = brw_vec4_grf(i, 0);
73 c->reg.vertex[j] = brw_vec4_grf(i, 0);
84 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
88 c->reg.t = brw_vec1_grf(i, 0);
89 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D);
90 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD);
91 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
92 c->reg.plane_equation = brw_vec4_grf(i, 4);
95 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 *
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUAsmPrinter.cpp | 74 unsigned reg; local
79 reg = MO.getReg();
80 if (reg == AMDGPU::VCC) {
84 if (reg == AMDGPU::EXEC) {
87 if (AMDGPU::SReg_32RegClass.contains(reg)) {
90 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
93 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
96 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
99 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
102 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
[all...] |
| SIRegisterInfo.cpp | 33 unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
35 switch (reg) {
38 default: return getHWRegNum(reg);
|
| /external/chromium_org/v8/src/ |
| code.h | 22 explicit ParameterCount(Register reg)
23 : reg_(reg), immediate_(0) { }
32 Register reg() const { function in class:v8::internal::BASE_EMBEDDED
|
| disasm.h | 18 virtual const char* NameOfCPURegister(int reg) const;
19 virtual const char* NameOfByteCPURegister(int reg) const;
20 virtual const char* NameOfXMMRegister(int reg) const;
|
| /external/libunwind/src/x86_64/ |
| Gregs.c | 32 linux_scratch_loc (struct cursor *c, unw_regnum_t reg)
39 return DWARF_REG_LOC (&c->dwarf, reg);
50 return DWARF_REG_LOC (&c->dwarf, reg);
55 x86_64_scratch_loc (struct cursor *c, unw_regnum_t reg)
58 return linux_scratch_loc (c, reg);
60 return DWARF_REG_LOC (&c->dwarf, reg);
65 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp,
72 switch (reg)
90 arg_num = reg - UNW_X86_64_RAX;
104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX]
[all...] |
