| /art/compiler/dex/quick/x86/ |
| target_x86.cc | 253 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
256 DCHECK(!lir->flags.use_def_invalid);
291 if (lir->opcode == kX86RepneScasw) {
333 std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
350 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands.
352 int operand = lir->operands[operand_number];
363 static_cast<uint32_t>(lir->operands[operand_number+1]));
383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand
[all...] |
| int_x86.cc | 96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
99 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ ,
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
106 int check_value, LIR* target) {
118 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc);
123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
133 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR
1615 LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), local
1650 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, local
2486 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); local
2518 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); local
2526 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); local
[all...] |
| assemble_x86.cc | 1599 LIR *lir; local
1900 LIR* lir; local
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 78 /* NOTE: must be kept in sync with enum ArmOpcode from LIR.h */
1211 LIR* lir; local
[all...] |
| target_arm.cc | 162 void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
165 DCHECK(!lir->flags.use_def_invalid);
167 int opcode = lir->opcode;
182 def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
186 def_mask->SetBits(EncodeArmRegList(lir->operands[1]));
190 def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
194 for (int i = 0; i < lir->operands[2]; i++) {
195 SetupRegMask(def_mask, lir->operands[1] + i);
209 use_mask->SetBits(EncodeArmRegList(lir->operands[0]))
[all...] |
| fp_arm.cc | 216 LIR* target = &block_label_list_[bb->taken];
311 LIR* it = OpIT((default_result == -1) ? kCondGt : kCondMi, "");
|
| /art/compiler/dex/quick/ |
| gen_invoke.cc | 45 void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) {
48 IntrinsicSlowPathPath(Mir2Lir* m2l, CallInfo* info, LIR* branch, LIR* resume = nullptr)
85 LIR* Mir2Lir::CallHelper(RegStorage r_tgt, QuickEntrypointEnum trampoline, bool safepoint_pc,
87 LIR* call_inst = InvokeTrampoline(use_link ? kOpBlx : kOpBx, r_tgt, trampoline);
766 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn,
[all...] |
| mir_to_lir.cc | 379 void Mir2Lir::CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) {
618 LIR* taken = &label_list[bb->taken];
619 LIR* fall_through = &label_list[bb->fall_through];
647 LIR* taken = &label_list[bb->taken];
648 LIR* fall_through = &label_list[bb->fall_through];
[all...] |
| ralloc_util.cc | 668 for (LIR* p = info->DefStart();; p = p->next) {
678 * Mark the beginning and end LIR of a def sequence. Note that
679 * on entry start points to the LIR prior to the beginning of the
682 void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) {
692 * Mark the beginning and end LIR of a def sequence. Note that
693 * on entry start points to the LIR prior to the beginning of the
696 void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 94 LoopIdiomRecognize &LIR;
308 LIR(TheLIR), CurLoop(TheLIR.getLoop()), PreCondBB(nullptr) {
312 const TargetTransformInfo *TTI = LIR.getTargetTransformInfo();
496 ScalarEvolution *SE = LIR.getScalarEvolution();
497 TargetLibraryInfo *TLI = LIR.getTargetLibraryInfo();
628 if (!LIR.getTargetTransformInfo())
631 LIR.getScalarEvolution();
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineTraceMetrics.cpp | 766 const LiveInReg &LIR = TBI.LiveIns[i];
767 if (!TargetRegisterInfo::isVirtualRegister(LIR.Reg))
769 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
774 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
[all...] |
| /art/compiler/dex/quick/arm64/ |
| target_arm64.cc | 166 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
169 DCHECK(!lir->flags.use_def_invalid);
335 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {
352 operand = lir->operands[nc-'0'];
357 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) :
407 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's',
411 bool is_wide = IS_WIDE(lir->opcode);
453 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4))
[all...] |
| fp_arm64.cc | 203 LIR* target = &block_label_list_[bb->taken];
|
