| /external/qemu/target-i386/ |
| ops_sse_header.h | 20 #define Reg MMXReg
23 #define Reg XMMReg
30 #define dh_ctype_Reg Reg *
37 DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
38 DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
39 DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg)
40 DEF_HELPER_3(glue(psrld, SUFFIX), void, env, Reg, Reg
[all...] |
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.h | 54 unsigned getFirstReg(unsigned Reg);
57 inline unsigned getRegAsGR64(unsigned Reg) {
58 return GR64Regs[getFirstReg(Reg)];
62 inline unsigned getRegAsGR32(unsigned Reg) {
63 return GR32Regs[getFirstReg(Reg)];
67 inline unsigned getRegAsGRH32(unsigned Reg) {
68 return GRH32Regs[getFirstReg(Reg)];
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 72 bool isAllocated(unsigned Reg) const {
73 return UsedRegs[Reg/32] & (1 << (Reg&31));
119 unsigned AllocateReg(unsigned Reg) {
120 if (isAllocated(Reg)) return 0;
121 MarkAllocated(Reg);
122 return Reg;
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
127 if (isAllocated(Reg)) return 0;
128 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcMachineFunctionInfo.h | 43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
48 VRegInfo[Reg].first = RC;
52 MachineRegisterInfo::constrainRegClass(unsigned Reg,
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
80 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
89 setRegClass(Reg, NewRC);
103 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| LivePhysRegs.cpp | 42 unsigned Reg = O->getReg();
43 if (Reg == 0)
45 removeReg(Reg);
54 unsigned Reg = O->getReg();
55 if (Reg == 0)
57 addReg(Reg);
70 unsigned Reg = O->getReg();
71 if (Reg == 0)
75 Defs.push_back(Reg);
80 removeReg(Reg);
[all...] |
| MachineInstrBundle.cpp | 133 unsigned Reg = MO.getReg();
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg = MO.getReg()
[all...] |
| CriticalAntiDepBreaker.cpp | 67 unsigned Reg = *AI;
68 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
69 KillIndices[Reg] = BBSize;
70 DefIndices[Reg] = ~0u;
82 unsigned Reg = *AI;
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
108 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
[all...] |
| AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| DeadMachineInstructionElim.cpp | 70 unsigned Reg = MO.getReg();
71 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
73 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
131 unsigned Reg = MO.getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(Reg))
134 MRI->markUsesInDebugValueAsUndef(Reg);
149 unsigned Reg = MO.getReg();
150 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 74 void addReg(unsigned Reg) {
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
84 void removeReg(unsigned Reg) {
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
90 for (MCSuperRegIterator SuperRegs(Reg, TRI, /*IncludeSelf=*/false);
98 /// \brief Returns true if register @p Reg is contained in the set. This also
99 /// works if only the super register of @p Reg has been defined, because we
101 bool contains(unsigned Reg) const { return LiveRegs.count(Reg);
[all...] |
| LiveVariables.h | 106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
[all...] |
| MachineRegisterInfo.h | 36 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
91 return MO->Contents.Reg.Next;
195 /// Verify the sanity of the use list for Reg.
196 void verifyUseList(unsigned Reg) const;
228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
244 reg_instructions(unsigned Reg) const {
245 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
261 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
[all...] |
| FunctionLoweringInfo.h | 154 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
155 if (!LiveOutRegInfo.inBounds(Reg))
158 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
170 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
173 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
179 LiveOutRegInfo.grow(Reg);
180 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
198 unsigned Reg = It->second;
199 LiveOutRegInfo.grow(Reg);
200 LiveOutRegInfo[Reg].IsValid = false
[all...] |
| RegisterScavenging.h | 45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
52 unsigned Reg;
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const {
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) const
[all...] |
| LiveIntervalAnalysis.h | 108 LiveInterval &getInterval(unsigned Reg) {
109 if (hasInterval(Reg))
110 return *VirtRegIntervals[Reg];
112 return createAndComputeVirtRegInterval(Reg);
115 const LiveInterval &getInterval(unsigned Reg) const {
116 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
119 bool hasInterval(unsigned Reg) const {
120 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
124 LiveInterval &createEmptyInterval(unsigned Reg) {
[all...] |
| StackMaps.h | 91 unsigned Reg;
93 Location() : LocType(Unprocessed), Size(0), Reg(0), Offset(0) {}
94 Location(LocationType LocType, unsigned Size, unsigned Reg, int64_t Offset)
95 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {}
99 unsigned short Reg;
103 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
104 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size)
105 : Reg(Reg), RegNo(RegNo), Size(Size) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.h | 36 unsigned getHWRegIndex(unsigned Reg) const override;
40 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
48 /// \returns A VGPR reg class with the same width as \p SRC
60 /// \returns The sub-register of Reg that is in Channel.
61 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
|
| R600RegisterInfo.h | 32 unsigned getHWRegChan(unsigned reg) const;
34 unsigned getHWRegIndex(unsigned Reg) const override;
43 // \returns true if \p Reg can be defined in one ALU caluse and used in another.
44 bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
|
| SIFixSGPRCopies.cpp | 89 unsigned Reg,
93 unsigned Reg,
130 /// This functions walks the use list of Reg until it finds an Instruction
136 unsigned Reg,
138 // The Reg parameter to the function must always be defined by either a PHI
140 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
141 "Reg cannot be a physical register");
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
162 unsigned Reg,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMachineFunctionInfo.h | 35 void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; }
40 void setHighSavedGPR(unsigned Reg) { HighSavedGPR = Reg; }
|
| SystemZShortenInst.cpp | 78 unsigned Reg = MI.getOperand(0).getReg();
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
110 unsigned Reg = *LI;
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112 LiveLow |= LowGPRs[Reg];
113 LiveHigh |= HighGPRs[Reg];
133 if (unsigned Reg = MO.getReg())
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const {
77 return MC->contains(Reg);
160 /// For all Reg in SuperRC:
161 /// this->contains(Reg:Idx)
225 // Pointer to array of lane masks, one per sub-reg index.
254 /// returns true if Reg is in the range used for stack slots.
260 static bool isStackSlot(unsigned Reg) {
261 return int(Reg) >= (1 << 30);
266 static int stackSlot2Index(unsigned Reg) {
267 assert(isStackSlot(Reg) && "Not a stack slot")
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 59 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
191 assert(Reg >= 0);
192 if (Reg < 32) {
193 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
194 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
197 Streamer.EmitULEB128(Reg, Twine(Reg));
202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
204 assert(Reg >= 0)
[all...] |
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
|
