| /external/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 236 unsigned Reg = MO->getReg();
239 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
240 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
243 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
245 MachineInstr *DefMI = MRI->getVRegDef(Reg);
291 unsigned Reg = MO->getReg();
292 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
294 // I clobbers Reg, so it isn't live before I.
296 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
298 // Unless I reads Reg
[all...] |
| RegAllocPBQP.cpp | 198 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
199 if (mri->def_empty(Reg))
201 pregs.insert(Reg);
202 mri->setPhysRegUsed(Reg);
444 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
445 if (mri->reg_nodbg_empty(Reg))
447 LiveInterval *li = &lis->getInterval(Reg);
453 vregsToAlloc.insert(li->reg);
[all...] |
| RegAllocGreedy.cpp | 198 return ExtraRegInfo[VirtReg.reg].Stage;
203 ExtraRegInfo[VirtReg.reg].Stage = Stage;
210 unsigned Reg = *Begin;
211 if (ExtraRegInfo[Reg].Stage == RS_New)
212 ExtraRegInfo[Reg].Stage = NewStage;
260 void reset(InterferenceCache &Cache, unsigned Reg) {
261 PhysReg = Reg;
263 Intf.setPhysReg(Cache, Reg);
498 // The queue holds (size, reg) pairs.
500 const unsigned Reg = LI->reg
[all...] |
| RegisterClassInfo.cpp | 57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 26 unsigned Reg;
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
151 Addr.Base.Reg = getRegForValue(Obj);
152 return Addr.Base.Reg != 0;
190 EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
239 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
|
| MipsSEFrameLowering.cpp | 324 unsigned Reg = I->getReg();
326 // If Reg is a double precision register, emit two cfa_offsets,
328 if (Mips::AFGR64RegClass.contains(Reg)) {
330 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
332 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
347 // Reg is either in GPR32 or FGR32.
349 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
371 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
373 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
463 unsigned Reg = CSI[i].getReg()
[all...] |
| MipsAsmPrinter.cpp | 263 unsigned Reg = CSI[i].getReg();
264 if (Mips::GPR32RegClass.contains(Reg))
267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
268 if (Mips::AFGR64RegClass.contains(Reg)) {
281 unsigned Reg = CSI[i].getReg();
282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
496 unsigned Reg = MO.getReg();
497 O << '$' << MipsInstPrinter::getRegisterName(Reg);
522 unsigned Reg = MO.getReg();
523 O << '$' << MipsInstPrinter::getRegisterName(Reg);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SILowerI1Copies.cpp | 144 for (unsigned Reg : I1Defs)
145 MRI.setRegClass(Reg, &AMDGPU::VReg_32RegClass);
|
| R600MachineScheduler.h | 87 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.6/sysroot/usr/include/X11/ |
| Xregion.h | 114 #define MEMCHECK(reg, rect, firstrect){\
115 if ((reg)->numRects >= ((reg)->size - 1)){\
117 ((char *)(firstrect), (unsigned) (2 * (sizeof(BOX)) * ((reg)->size)));\
120 (reg)->size *= 2;\
121 (rect) = &(firstrect)[(reg)->numRects];\
129 #define CHECK_PREVIOUS(Reg, R, Rx1, Ry1, Rx2, Ry2)\
130 (!(((Reg)->numRects > 0)&&\
137 #define ADDRECT(reg, r, rx1, ry1, rx2, ry2){\
139 CHECK_PREVIOUS((reg), (r), (rx1), (ry1), (rx2), (ry2))){
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/X11/ |
| Xregion.h | 114 #define MEMCHECK(reg, rect, firstrect){\
115 if ((reg)->numRects >= ((reg)->size - 1)){\
117 ((char *)(firstrect), (unsigned) (2 * (sizeof(BOX)) * ((reg)->size)));\
120 (reg)->size *= 2;\
121 (rect) = &(firstrect)[(reg)->numRects];\
129 #define CHECK_PREVIOUS(Reg, R, Rx1, Ry1, Rx2, Ry2)\
130 (!(((Reg)->numRects > 0)&&\
137 #define ADDRECT(reg, r, rx1, ry1, rx2, ry2){\
139 CHECK_PREVIOUS((reg), (r), (rx1), (ry1), (rx2), (ry2))){
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 71 OS << markup("<reg:")
267 // a single GPRPair reg operand is used in the .td file to replace the two
275 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
276 if (MRC.contains(Reg)) {
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
303 unsigned Reg = Op.getReg();
304 printRegName(O, Reg);
369 // REG 0 0 - e.g. R5
370 // REG REG 0,SH_OPC - e.g. R5, ROR R
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 42 unsigned Reg;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 36 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMELFStreamer.cpp | 124 void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
176 void ARMTargetAsmStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
177 assert((Reg != ARM::SP && Reg != ARM::PC) &&
181 InstPrinter.printRegName(OS, Reg);
398 void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
464 void emitMovSP(unsigned Reg, int64_t Offset = 0);
672 void ARMTargetELFStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
673 getStreamer().emitMovSP(Reg, Offset);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 85 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 115 SDValue Reg;
122 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
125 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
129 OutOps.push_back(Reg);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineFrameInfo.h | 38 unsigned Reg;
43 : Reg(R), FrameIdx(FI) {}
46 unsigned getReg() const { return Reg; }
|
| MachineInstrBuilder.h | 352 unsigned Reg,
357 .addReg(Reg, RegState::Debug)
363 .addReg(Reg, RegState::Debug)
378 unsigned Reg,
382 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 249 bool baseRegNeedsLoadStoreMask(unsigned Reg) {
251 return Reg != Mips::SP && Reg != Mips::T8;
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 79 unsigned SystemZMC::getFirstReg(unsigned Reg) {
93 assert(Reg < SystemZ::NUM_TARGET_REGS);
94 return Map[Reg];
|
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 104 static bool isYmmReg(unsigned Reg) {
105 return (Reg >= X86::YMM0 && Reg <= X86::YMM15);
118 for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) {
119 if (!MO.clobbersPhysReg(reg))
148 for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 134 unsigned Reg = MO.getReg();
135 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if(ARM::GPRPairRegClass.contains(Reg)) {
140 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
142 O << ARMInstPrinter::getRegisterName(Reg);
231 unsigned Reg = MI->getOperand(OpNum).getReg();
235 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
238 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
321 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q'
[all...] |
| ARMLoadStoreOptimizer.cpp | 85 unsigned Reg;
92 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
435 // VLDM/VSTM do not support DB mode without also updating the base reg.
504 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
632 unsigned Reg = memOps[i].Reg;
633 KilledRegs.insert(Reg);
634 Killer[Reg] = i;
642 unsigned Reg = memOps[i].Reg;
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 214 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
215 unsigned SEH = MRI->getEncodingValue(Reg);
216 MRI->mapLLVMRegToSEHReg(Reg, SEH);
|
