| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 29 const CodeGenRegister *Reg = T.getRegBank().getReg(R);
34 if (!RC.contains(Reg))
189 true/*Ignore reg constraints*/);
376 // "(add reg, (load ptr))" as a add_with_memory on X86). This is
377 // problematic, if the 'reg' node also uses the load (say, its chain).
625 const CodeGenRegister *Reg =
627 AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0)));
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 413 unsigned Reg = VA.getLocReg();
417 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
419 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
420 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
426 Reg = MF.addLiveIn(Reg, RC);
427 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT)
[all...] |
| R600ControlFlowFinalizer.cpp | 289 unsigned Reg = MO.getReg();
290 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
291 DstMI = Reg;
293 DstMI = TRI->getMatchingSuperReg(Reg,
294 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
298 unsigned Reg = MO.getReg();
299 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
300 SrcMI = Reg;
302 SrcMI = TRI->getMatchingSuperReg(Reg,
303 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
[all...] |
| SILowerControlFlow.cpp | 182 unsigned Reg = MI.getOperand(0).getReg();
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
188 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
190 .addReg(Reg);
279 unsigned Reg = MI.getOperand(0).getReg();
284 .addReg(Reg);
|
| /external/llvm/lib/CodeGen/ |
| IfConversion.cpp | [all...] |
| RegisterCoalescer.cpp | 151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
479 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
499 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
507 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
614 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
622 // If some of the uses of IntA.reg is already coalesced away, return false.
624 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 48 // we may not actually need both reg and (-1 * reg) in registers; the
143 void CountRegister(const SCEV *Reg, size_t LUIdx);
144 void DropRegister(const SCEV *Reg, size_t LUIdx);
147 bool isRegUsedByUsesOtherThan(const SCEV *Reg, size_t LUIdx) const;
149 const SmallBitVector &getUsedByIndices(const SCEV *Reg) const;
164 RegUseTracker::CountRegister(const SCEV *Reg, size_t LUIdx) {
166 RegUsesMap.insert(std::make_pair(Reg, RegSortData()));
169 RegSequence.push_back(Reg);
175 RegUseTracker::DropRegister(const SCEV *Reg, size_t LUIdx)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_optimize.c | 297 /* check dst reg */
526 /* Walk through remaining instructions until the or src reg gets
842 GLuint Reg; /** The temporary register index */
893 if (list->Intervals[k].Reg == inv->Reg) {
1078 inv.Reg = i;
1092 printf("Reg[%d] live [%d, %d]:",
1093 inv->Reg, inv->Start, inv->End);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119 if (TargetRegisterInfo::isVirtualRegister(Reg))
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
127 PhysReg = Reg;
129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
533 // Check for phys reg copy.
641 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
642 if (TargetRegisterInfo::isVirtualRegister(Reg))
655 dbgs() << "PHYS REG COPY\n";
768 unsigned Reg = 0
[all...] |
| SelectionDAGBuilder.h | 238 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
240 /// Reg - the virtual register containing the index of the jump table entry
242 unsigned Reg;
280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
285 unsigned Reg;
588 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
683 unsigned Reg,
|
| /external/mesa3d/src/mesa/program/ |
| prog_optimize.c | 297 /* check dst reg */
526 /* Walk through remaining instructions until the or src reg gets
842 GLuint Reg; /** The temporary register index */
893 if (list->Intervals[k].Reg == inv->Reg) {
1078 inv.Reg = i;
1092 printf("Reg[%d] live [%d, %d]:",
1093 inv->Reg, inv->Start, inv->End);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 86 void saveFPReg(int Reg) { FPReg = Reg; }
521 struct RegOp Reg;
552 Reg = o.Reg;
643 return Reg.RegNum;
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 237 struct RegOp Reg;
283 Reg = o.Reg;
353 return Reg.RegNum;
880 bool isReg() const override { return Kind == k_Register && !Reg.isVector; }
881 bool isVectorReg() const { return Kind == k_Register && Reg.isVector; }
883 return Kind == k_Register && Reg.isVector &&
885 Reg.RegNum);
888 return Kind == k_Register && !Reg.isVector &&
889 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 559 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
568 // FIXME: How do we know Base.Reg is free??
569 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
578 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
579 AM.Base.Reg = X86::RIP;
596 StubAM.Base.Reg = AM.Base.Reg;
608 StubAM.Base.Reg = X86::RIP;
628 AM.Base.Reg = LoadReg;
636 if (AM.Base.Reg == 0)
[all...] |
| X86MCInstLower.cpp | 249 unsigned Reg = Inst.getOperand(0).getReg();
250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
310 unsigned Reg = Inst.getOperand(RegOp).getReg();
311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
263 if (!MRI.isLiveOut(Reg)) {
264 MRI.addLiveOut(Reg);
266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
|
| AMDGPUISelLowering.cpp | 315 unsigned Reg, EVT VT) const {
319 if (!MRI.isLiveIn(Reg)) {
321 MRI.addLiveIn(Reg, VirtualRegister);
323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 428 /// \brief All possible values of the reg field in the ModR/M byte.
429 enum Reg {
578 Reg vvvv;
581 Reg writemask;
602 Reg opcodeRegister;
610 Reg regBase;
616 // The reg field always encodes a register
617 Reg reg; member in struct:llvm::X86Disassembler::InternalInstruction
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
263 if (!MRI.isLiveOut(Reg)) {
264 MRI.addLiveOut(Reg);
266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 29 inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
66 return Reg;
69 inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
106 return Reg;
109 static inline unsigned getBRegFromDReg(unsigned Reg) {
110 switch (Reg) {
145 return Reg;
149 static inline unsigned getDRegFromBReg(unsigned Reg) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 120 /// If successful, it will return true and set the \p Reg, \p IVBump
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
236 unsigned Reg;
246 Contents.R.Reg = v;
257 return Contents.R.Reg;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
320 unsigned &Reg,
348 // latch block, and see if is a result of an addition of form "reg+imm",
349 // where the "reg" is defined by the PHI node we are looking at.
416 Reg = F->second.first
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 196 unsigned Reg = CSI[i-1].getReg();
198 MBB.addLiveIn(Reg);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
106 unsigned Reg = MI->getOperand(0).getReg();
107 bool IsHigh = isHighReg(Reg);
140 unsigned Reg = MI->getOperand(0).getReg();
141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
417 // If Reg is a virtual register, return its definition, otherwise return null.
418 static MachineInstr *getDef(unsigned Reg,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 40 /// the source reg along with the FrameIndex of the loaded stack slot. If
91 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
|
