| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 65 void EmitInstrReg(unsigned Opcode, unsigned Reg);
|
| MipsISelLowering.cpp | 563 // load $reg, x
564 // movz $reg, $0, a
[all...] |
| MipsSEInstrInfo.cpp | 62 /// the source reg along with the FrameIndex of the loaded stack slot. If
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
371 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
377 /// result of adding register REG and immediate IMM.
401 unsigned Reg = RegInfo.createVirtualRegister(RC)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 211 bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
213 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
214 return RC->contains(Reg);
216 return MRI->getRegClass(Reg) == RC;
416 // Flush physical reg copies (RA will discard them)
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| SIISelLowering.h | 79 unsigned Reg, EVT VT) const override;
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| R600InstrInfo.cpp | 315 unsigned Reg = MO.getReg();
316 if (Reg == AMDGPU::ALU_CONST) {
338 unsigned Reg = MI->getOperand(SrcIdx).getReg();
339 if (Reg == AMDGPU::ALU_CONST) {
345 if (Reg == AMDGPU::ALU_LITERAL_X) {
366 unsigned Reg = Srcs[i].first->getReg();
367 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
368 if (Reg == AMDGPU::OQAP) {
371 if (PV.find(Reg) != PV.end()) {
372 // 255 is used to tells its a PS/PV reg
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 81 /// the source reg along with the FrameIndex of the loaded stack slot. If
365 llvm_unreachable("Impossible reg-to-reg copy");
443 unsigned Reg, uint64_t Value) const {
449 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
453 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value);
459 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 149 // Return the sub-register index naming Reg as a sub-register of this
150 // register. Returns NULL if Reg is not a sub-register.
151 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
152 return SubReg2Idx.lookup(Reg);
262 // Map SubRegIndex -> set of super-reg classes. This is all register
559 unsigned getRegIndex(const CodeGenRegister *Reg) const {
560 return Reg->EnumValue - 1;
571 // Others should simply use Reg->getTopoSig().
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 315 unsigned Reg, EVT VT) const {
319 if (!MRI.isLiveIn(Reg)) {
321 MRI.addLiveIn(Reg, VirtualRegister);
323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
74 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
237 void releaseInterferences(unsigned Reg = 0);
291 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
669 // Check for phys reg copy.
[all...] |
| /external/llvm/include/llvm/Support/ |
| ARMWinEH.h | 40 /// | Stack Adjust |C|L|R| Reg |H|Ret| Function Length |Flg|
61 /// Reg : 3-bit field indicating the index of the last saved non-volatile
63 /// saved (r4-rN, where N is 4 + Reg). If the R bit is set to 1, then
65 /// 8 + Reg). The special case of the R bit being set to 1 and Reg equal
69 /// special case of the R-flag being set and Reg being set to 7 indicates
90 /// + r11 must NOT be included in the set of registers described by Reg
148 uint8_t Reg() const {
172 assert(((~UnwindData & 0x00200000) || (Reg() < 7) || R()) &&
173 "r11 must not be included in Reg; C implies r11")
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 59 void CCState::MarkAllocated(unsigned Reg) {
60 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
|
| TargetSchedule.cpp | 269 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
74 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 210 static inline bool isARMLowRegister(unsigned Reg) {
212 switch (Reg) {
|
| ARMUnwindOpAsm.cpp | 156 void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
157 EmitInt8(ARM::EHABI::UNWIND_OPCODE_SET_VSP | Reg);
|
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 86 unsigned Reg = Op.getReg();
87 printRegName(O, Reg);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 81 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
83 MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
|
| /external/qemu-pc-bios/bochs/bios/ |
| notes | 24 * drive sets the busy bit in Status Reg to 1
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 245 unsigned Reg = MO.getReg();
247 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
249 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
251 LV->addVirtualRegisterDead(Reg, NewMI);
257 if (!NewMI->readsRegister(Reg))
259 LV->addVirtualRegisterKilled(Reg, NewMI);
747 assert(Opc && "Impossible reg-to-reg copy");
752 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
784 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 320 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
329 void removeLiveIn(unsigned Reg);
333 bool isLiveIn(unsigned Reg) const;
621 /// computeRegisterLiveness - Return whether (physical) register \c Reg
628 /// \c Reg must be a physical register.
630 unsigned Reg, MachineInstr *MI,
|
| /external/llvm/lib/MC/MCAnalysis/ |
| MCModuleYAML.cpp | 67 bool matchRegister(StringRef Name, unsigned &Reg) {
71 Reg = It->getValue();
242 unsigned Reg;
243 if (!IRI->matchRegister(Scalar.substr(1), Reg))
245 Val.MCOp = MCOperand::CreateReg(Reg);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 223 unsigned Reg = I.getOperand(oi).getReg();
225 assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
226 HeadReg = Reg;
229 assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
230 CmpBBReg = Reg;
247 // PHI operands are (Reg, MBB) at (oi-2, oi-1).
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.cpp | 372 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
1242 uint8_t mod, rm, reg; local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 116 unsigned Reg = DefMO.getReg();
120 if (TRI->isVirtualRegister(Reg)) {
123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
126 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
127 PPC::CRBITRCRegClass.contains(Reg);
760 llvm_unreachable("Impossible reg-to-reg copy");
[all...] |
