| /external/valgrind/main/VEX/priv/ |
| host_amd64_defs.c | 47 void ppHRegAMD64 ( HReg reg )
54 if (hregIsVirtual(reg)) {
55 ppHReg(reg);
59 switch (hregClass(reg)) {
61 r = hregNumber(reg);
66 r = hregNumber(reg);
71 r = hregNumber(reg);
80 static void ppHRegAMD64_lo32 ( HReg reg )
87 if (hregIsVirtual(reg)) {
88 ppHReg(reg);
2276 UInt reg; local
[all...] |
| /external/llvm/utils/TableGen/ |
| AsmMatcherEmitter.cpp | 382 static ResOperand getRegOp(Record *Reg) {
385 X.Register = Reg;
787 if (Record *Reg = AsmOperands[i].SingletonReg)
788 SingletonRegisters.insert(Reg);
[all...] |
| AsmWriterEmitter.cpp | 529 const CodeGenRegister &Reg = *Registers[i];
535 AsmName = Reg.TheDef->getValueAsString("AsmName");
537 AsmName = Reg.getName();
541 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
551 Reg.TheDef->getValueAsListOfStrings("AltNames");
553 PrintFatalError(Reg.TheDef->getLoc(),
[all...] |
| DAGISelMatcher.h | 878 /// Reg - The def for the register that we're emitting. If this is null, then
880 const CodeGenRegister *Reg;
883 EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt)
884 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
886 const CodeGenRegister *getReg() const { return Reg; }
896 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
900 return ((unsigned)(intptr_t)Reg) << 4 | VT;
[all...] |
| DAGISelMatcherEmitter.cpp | 455 const CodeGenRegister *Reg = Matcher->getReg();
458 if (Reg && Reg->EnumValue > 255) {
460 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
464 if (Reg) {
465 OS << getQualifiedName(Reg->TheDef) << ",\n";
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
531 SavedRegs[SavedRegIdx++] = Reg;
610 int getCompactUnwindRegNum(unsigned Reg) const {
619 if (*CURegs == Reg)
633 unsigned Reg = SavedRegs[i];
634 if (Reg == 0) break;
636 int CURegNum = getCompactUnwindRegNum(Reg);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 136 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
207 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
210 unsigned Reg, MachineRegisterInfo *MRI) const override;
388 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 153 unsigned Reg = II->getOperand(i).getReg();
158 if (localBegin->modifiesRegister(Reg, TRI) ||
159 localBegin->readsRegister(Reg, TRI))
288 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
307 if (reg >= 0)
325 if (reg >= 0)
390 unsigned predReg = 0; // predicate reg of the jump.
491 // We need cmpReg1 and cmpOp2(imm or reg) while building
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 32 /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list
34 /// Reg.
36 unsigned Reg, EVT VT) const;
|
| AMDGPUInstrInfo.cpp | 165 unsigned Reg, bool UnfoldLoad,
|
| AMDGPUInstrInfo.h | 102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 133 unsigned getReg() const { return getParent().reg; }
209 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
211 void eraseVirtReg(unsigned Reg);
|
| SelectionDAG.h | 474 SDValue getRegister(unsigned Reg, EVT VT);
486 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) {
488 getRegister(Reg, N.getValueType()), N);
494 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N,
497 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
502 // Similar to last getCopyToReg() except parameter Reg is a SDValue
503 SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N,
506 SDValue Ops[] = { Chain, Reg, N, Glue };
511 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
513 SDValue Ops[] = { Chain, getRegister(Reg, VT) }
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 172 int regIndex(unsigned Reg);
205 int ExeDepsFix::regIndex(unsigned Reg) {
206 assert(Reg < AliasMap.size() && "Invalid register");
207 return AliasMap[Reg];
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.h | 116 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
| SIInstrInfo.cpp | 395 unsigned Reg = MI->getOperand(1).getReg();
398 MI->getOperand(2).ChangeToRegister(Reg, false);
586 unsigned Reg = MI->getOperand(i).getReg();
587 if (TargetRegisterInfo::isVirtualRegister(Reg))
591 if (!RC->contains(Reg)) {
772 unsigned Reg = MRI.createVirtualRegister(VRC);
774 Reg).addOperand(MO);
775 MO.ChangeToRegister(Reg, false);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 32 /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list
34 /// Reg.
36 unsigned Reg, EVT VT) const;
|
| AMDGPUInstrInfo.cpp | 165 unsigned Reg, bool UnfoldLoad,
|
| AMDGPUInstrInfo.h | 102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 107 unsigned Reg) const {
110 switch (Reg) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList, 6))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
92 unsigned Reg = 0;
96 Reg = SP::I0 + Offset/8;
99 Reg = SP::D0 + Offset/8;
102 Reg = SP::F1 + Offset/4
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| Win64EHDumper.cpp | 73 static StringRef getUnwindRegisterName(uint8_t Reg) {
74 switch (Reg) {
183 OS << " reg=" << getUnwindRegisterName(UC[0].getOpInfo());
198 OS << " reg=<invalid>";
200 OS << " reg=" << getUnwindRegisterName(UI.getFrameRegister())
205 OS << " reg=" << getUnwindRegisterName(UC[0].getOpInfo())
210 OS << " reg=" << getUnwindRegisterName(UC[0].getOpInfo())
215 OS << " reg=XMM" << static_cast<uint32_t>(UC[0].getOpInfo())
220 OS << " reg=XMM" << static_cast<uint32_t>(UC[0].getOpInfo())
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/distutils/ |
| msvc9compiler.py | 64 class Reg:
134 self.macros["$(%s)" % macro] = Reg.get_value(path, key)
164 d = Reg.get_value(base, r"%s\%s" % (p, key))
227 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase,
236 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase,
283 line = Reg.convert_mbcs(line)
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/distutils/ |
| msvc9compiler.py | 64 class Reg:
134 self.macros["$(%s)" % macro] = Reg.get_value(path, key)
164 d = Reg.get_value(base, r"%s\%s" % (p, key))
227 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase,
236 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase,
283 line = Reg.convert_mbcs(line)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 71 unsigned Reg;
80 Base.Reg = 0;
382 if (Addr.Base.Reg == 0)
383 Addr.Base.Reg = getRegForValue(Obj);
387 if (Addr.Base.Reg != 0)
388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
390 return Addr.Base.Reg != 0;
410 Addr.Base.Reg = ResultReg;
503 // Base reg with offset in range.
507 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
[all...] |
