| /external/mesa3d/src/glsl/ |
| ast_to_hir.cpp | 62 exec_list *instructions);
65 _mesa_ast_to_hir(exec_list *instructions, struct _mesa_glsl_parse_state *state)
67 _mesa_glsl_initialize_variables(instructions, state);
73 state->toplevel_ir = instructions;
91 ast->hir(instructions, state);
93 detect_recursion_unlinked(state, instructions);
94 detect_conflicting_assignments(state, instructions);
672 do_assignment(exec_list *instructions, struct _mesa_glsl_parse_state *state,
762 instructions->push_tail(var);
763 instructions->push_tail(new(ctx) ir_assignment(deref_var, rhs))
[all...] |
| ir_basic_block.cpp | 52 void call_for_basic_blocks(exec_list *instructions,
61 foreach_iter(exec_list_iterator, iter, *instructions) {
89 * maximal BBs between the instructions that precede main()
90 * and the body of main(). Perhaps those instructions ought
|
| lower_texture_projection.cpp | 92 do_lower_texture_projection(exec_list *instructions)
96 visit_list_elements(&v, instructions);
|
| opt_array_splitting.cpp | 101 bool get_split_list(exec_list *instructions, bool linked);
195 * so just look at the body instructions and not the parameter
203 ir_array_reference_visitor::get_split_list(exec_list *instructions,
206 visit_list_elements(this, instructions);
212 foreach_list(node, instructions) {
356 optimize_split_arrays(exec_list *instructions, bool linked)
359 if (!refs.get_split_list(instructions, linked))
396 visit_list_elements(&split, instructions);
399 _mesa_print_ir(instructions, NULL);
|
| opt_if_simplification.cpp | 50 /* We only care about the top level "if" instructions, so don't
61 do_if_simplification(exec_list *instructions)
65 v.run(instructions);
|
| opt_redundant_jumps.cpp | 49 /* We only care about the top level instructions, so don't descend
118 optimize_redundant_jumps(exec_list *instructions)
122 v.run(instructions);
|
| opt_swizzle_swizzle.cpp | 90 do_swizzle_swizzle(exec_list *instructions)
94 v.run(instructions);
|
| /build/core/combo/arch/mips/ |
| mips32r2-fp-xburst.mk | 3 # support for the Madd family of instructions.
|
| /external/chromium_org/third_party/mesa/src/src/glsl/ |
| ir_basic_block.cpp | 52 void call_for_basic_blocks(exec_list *instructions,
61 foreach_iter(exec_list_iterator, iter, *instructions) {
89 * maximal BBs between the instructions that precede main()
90 * and the body of main(). Perhaps those instructions ought
|
| lower_texture_projection.cpp | 92 do_lower_texture_projection(exec_list *instructions)
96 visit_list_elements(&v, instructions);
|
| opt_array_splitting.cpp | 101 bool get_split_list(exec_list *instructions, bool linked);
195 * so just look at the body instructions and not the parameter
203 ir_array_reference_visitor::get_split_list(exec_list *instructions,
206 visit_list_elements(this, instructions);
212 foreach_list(node, instructions) {
356 optimize_split_arrays(exec_list *instructions, bool linked)
359 if (!refs.get_split_list(instructions, linked))
396 visit_list_elements(&split, instructions);
399 _mesa_print_ir(instructions, NULL);
|
| opt_if_simplification.cpp | 50 /* We only care about the top level "if" instructions, so don't
61 do_if_simplification(exec_list *instructions)
65 v.run(instructions);
|
| opt_redundant_jumps.cpp | 49 /* We only care about the top level instructions, so don't descend
118 optimize_redundant_jumps(exec_list *instructions)
122 v.run(instructions);
|
| opt_swizzle_swizzle.cpp | 90 do_swizzle_swizzle(exec_list *instructions)
94 v.run(instructions);
|
| /external/llvm/test/MC/ARM/ |
| fp-const-errors.s | 10 @ Test that vmov.f instructions do not accept an 8-bit encoded float as an operand
17 @ Test that fconst instructions do not accept a float constant as an operand
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 0 # Instructions that are valid
17 # FIXME: Add the instructions carried forward from older ISA's
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 0 # Instructions that are valid
17 # FIXME: Add the instructions carried forward from older ISA's
|
| /libcore/luni/src/test/java/libcore/xml/ |
| SimpleParserTest.java | 41 private StringBuffer instructions; field in class:SimpleParserTest
63 instructions = new StringBuffer();
75 instructions = null;
99 if (instructions.length() != 0) {
100 instructions.append(",");
102 instructions.append(s);
158 assertEquals("The:quick,brown:fox", instructions.toString());
186 assertEquals("The:quick,brown:fox", instructions.toString());
|
| /external/oprofile/events/mips/25K/ |
| events | 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
20 event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only)
29 event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack
50 event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cach
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions complete
[all...] |
| /external/oprofile/events/mips/74K/ |
| events | 15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
35 event:0x11 counters:0,2 um:zero minimum:500 name:ALU_OPERANDS_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
36 event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy
40 event:0x16 counters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions
41 event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
[all...] |
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/ |
| MethodDefinition.java | 66 @Nonnull public final ImmutableList<Instruction> instructions; field in class:MethodDefinition
85 instructions = ImmutableList.copyOf(methodImpl.getInstructions());
90 instructionOffsetMap = new InstructionOffsetMap(instructions);
92 for (int i=0; i<instructions.size(); i++) {
93 Instruction instruction = instructions.get(i);
219 Instruction instruction = instructions.get(targetIndex);
224 if (targetIndex < instructions.size()) {
225 instruction = instructions.get(targetIndex);
330 for (int i=0; i<instructions.size(); i++) {
331 Instruction instruction = instructions.get(i)
399 List<AnalyzedInstruction> instructions = methodAnalyzer.getAnalyzedInstructions(); local
[all...] |
| /external/elfutils/0.153/libdw/ |
| fde.c | 101 fde->instructions = entry->start;
104 &fde->instructions, &fde->start))
106 &fde->instructions, &fde->end)))
117 get_uleb128 (len, fde->instructions);
118 if ((Dwarf_Word) (fde->instructions_end - fde->instructions) < len)
124 fde->instructions += len;
129 fde->instructions += cie->fde_augmentation_data_size;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_fs_schedule_instructions.cpp | 35 * List scheduling of FS instructions.
120 this->instructions.make_empty();
142 exec_list instructions; member in class:instruction_scheduler
157 instructions.push_tail(n);
266 schedule_node *last = (schedule_node *)instructions.get_tail();
273 foreach_list(node, &instructions) {
355 for (node = instructions.get_tail(), prev = node->prev;
436 foreach_list_safe(node, &instructions) {
442 while (!instructions.is_empty()) {
446 foreach_list(node, &instructions) {
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_schedule_instructions.cpp | 35 * List scheduling of FS instructions.
120 this->instructions.make_empty();
142 exec_list instructions; member in class:instruction_scheduler
157 instructions.push_tail(n);
266 schedule_node *last = (schedule_node *)instructions.get_tail();
273 foreach_list(node, &instructions) {
355 for (node = instructions.get_tail(), prev = node->prev;
436 foreach_list_safe(node, &instructions) {
442 while (!instructions.is_empty()) {
446 foreach_list(node, &instructions) {
[all...] |
