| /external/llvm/test/MC/ARM/ |
| eh-directive-section-multiple-func.s | 52 @ Check the .TEST1 section. There should be two "bx lr" instructions.
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding-vmx.s | 7 # Vector storage access instructions
46 # Vector permute and formatting instructions
156 # Vector integer arithmetic instructions
346 # Vector integer compare instructions
403 # Vector integer logical instructions
421 # Vector integer rotate and shift instructions
461 # Vector floating-point instructions
546 # Vector status and control register instructions
|
| /external/llvm/utils/ |
| codegen-diff | 116 Don't show instructions where the bytes are different but they
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_live_variables.cpp | 185 foreach_list(node, &this->instructions) {
|
| brw_vec4_copy_propagation.cpp | 208 * vec8s into gen6 math instructions, because of the weird src
209 * handling for those instructions. Just ignore them for now.
240 foreach_list(node, &this->instructions) {
|
| brw_context.h | 740 * fragment shader instructions.
[all...] |
| /external/sonivox/arm-hybrid-22k/lib_src/ |
| ARM-E_voice_gain_gnu.s | 79 @ NOTE: instructions are reordered to reduce the effect of latency
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| ARM-E_voice_gain_gnu.s | 79 @ NOTE: instructions are reordered to reduce the effect of latency
|
| /external/speex/libspeex/ |
| arch.h | 68 #error I suppose you can have a [ARM4/ARM5E/Blackfin] that has float instructions?
|
| /external/webrtc/src/modules/audio_coding/codecs/isac/fix/source/ |
| lattice_neon.S | 29 @ instructions, smulwb, and smull. Speech quality was not degraded by
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/ |
| pprof | [all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| ir_to_mesa.cpp | 197 * At the point that Mesa instructions for function calls are
281 exec_list instructions; member in class:ir_to_mesa_visitor
382 this->instructions.push_tail(inst);
939 new_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1164 * older GPUs implement SEQ using multiple instructions (i915 uses two
1165 * SGE instructions and a MUL instruction). Since our logic values are
[all...] |
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 197 * At the point that Mesa instructions for function calls are
281 exec_list instructions; member in class:ir_to_mesa_visitor
382 this->instructions.push_tail(inst);
939 new_inst = (ir_to_mesa_instruction *)this->instructions.get_tail();
1164 * older GPUs implement SEQ using multiple instructions (i915 uses two
1165 * SGE instructions and a MUL instruction). Since our logic values are
[all...] |
| /build/tools/droiddoc/templates-pdk/assets/design/ |
| default.css | 613 .video-instructions {
616 .video-instructions:before {
623 .video-instructions:after {
|
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 429 ; One operand instructions
457 ; 6.6.1 Multiply-add instructions
479 ; Multiply-high instructions
489 ; Move immediate instructions
523 ; Conditionally set flags instructions
547 ; Conditional select instructions
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| MethodAnalyzer.java | 62 * The MethodAnalyzer performs several functions. It "analyzes" the instructions and infers the register types
63 * for each register, it can deodex odexed instructions, and it can verify the bytecode. The analysis and verification
64 * are done in two separate passes, because the analysis has to process instructions multiple times in some cases, and
84 // Which instructions have been analyzed, keyed by instruction index
91 //successors, e.g. the first real instruction, the first instructions in any exception handlers covering the first
177 //make sure all of the "first instructions" are marked for processing
241 //Now, go through and fix up any unresolvable odex instructions. These are usually odex instructions
387 ImmutableList<Instruction> instructions = ImmutableList.copyOf(methodImpl.getInstructions());
389 analyzedInstructions.ensureCapacity(instructions.size())
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glsl/ |
| lower_jumps.cpp | 76 * instructions as either break, continue, return, or other. When
83 * - It ignores discard instructions, since they are lowered by a
308 * Insert the instructions necessary to lower a return statement,
329 * If the given instruction is a return, lower it to instructions
390 /* Eliminate all instructions after each one, since they are
412 /* Eliminate all instructions after each one, since they are
624 * function doesn't have one already) and add instructions
731 /* Now we need to clean up the instructions that follow the
734 * If those instructions are unreachable, then satisfy the
743 * we need to guard any instructions that follow so that the
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_context.h | 740 * fragment shader instructions.
[all...] |
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| org.eclipse.equinox.p2.metadata.repository_1.1.0.v20100513.jar | |
| /external/libcxxabi/src/Unwind/ |
| UnwindRegistersRestore.S | 343 @ VFP and iwMMX instructions are only available when compiling with the flags
345 @ want the compiler to generate instructions that access those) but this is
|
| UnwindRegistersSave.S | 343 @ VFP and iwMMX instructions are only available when compiling with the flags
345 @ want the compiler to generate instructions that access those) but this is
349 @ So, generate the instructions using the corresponding coprocessor mnemonic.
|
| /external/lldb/examples/python/ |
| symbolication.py | 471 def disassemble_instructions (target, instructions, pc, insts_before_pc, insts_after_pc, non_zeroeth_frame):
475 for inst_idx, inst in enumerate(instructions):
|
| /external/llvm/test/MC/Mips/ |
| micromips-alu-instructions.s | 4 # for arithmetic and logical instructions.
6 # Arithmetic and Logical Instructions
|
| /external/llvm/utils/TableGen/ |
| InstrInfoEmitter.cpp | 180 for (const CodeGenInstruction *Inst : Target.instructions()) {
199 /// each instructions. This is used to generate the OperandMap table as
361 for (const CodeGenInstruction *II : Target.instructions()) {
559 // emitEnums - Print out enum values for all of the instructions.
573 fprintf(stderr, "No instructions defined!\n");
|
| /external/mesa3d/src/glsl/ |
| lower_jumps.cpp | 76 * instructions as either break, continue, return, or other. When
83 * - It ignores discard instructions, since they are lowered by a
308 * Insert the instructions necessary to lower a return statement,
329 * If the given instruction is a return, lower it to instructions
390 /* Eliminate all instructions after each one, since they are
412 /* Eliminate all instructions after each one, since they are
624 * function doesn't have one already) and add instructions
731 /* Now we need to clean up the instructions that follow the
734 * If those instructions are unreachable, then satisfy the
743 * we need to guard any instructions that follow so that the
[all...] |
