HomeSort by relevance Sort by last modified time
    Searched refs:prefetch (Results 26 - 50 of 134) sorted by null

12 3 4 5 6

  /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/
processor.h 29 #include <asm/prefetch.h>
  /external/clang/test/CodeGen/
builtins.c 29 V(prefetch, (&N));
30 V(prefetch, (&N, 1));
31 V(prefetch, (&N, 1, 0));
  /external/oprofile/events/i386/atom/
events 15 event:0x07 counters:0,1 um:simd_prefetch minimum:6000 name:PREFETCH : Streaming SIMD Extensions (SSE) Prefetch instructions executed
25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
27 event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted
28 event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache
30 event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads
33 event:0x2E counters:0,1 um:l2_rqsts,core,prefetch,mesi minimum:6000 name:L2_RQSTS : L2 cache requests
34 event:0x30 counters:0,1 um:core,prefetch,mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache requests
unit_masks 12 0x08 prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
111 name:prefetch type:bitmask default:0x60
113 0x20 hw Hardware prefetch only
114 0x00 exclude_hw Exclude hardware prefetch
  /external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/
sha256-mips.S 779 lw $8,0($29) # prefetch from ring buffer
832 lw $9,4($29) # prefetch from ring buffer
883 lw $10,8($29) # prefetch from ring buffer
951 lw $11,12($29) # prefetch from ring buffer
1016 lw $12,16($29) # prefetch from ring buffer
1081 lw $13,20($29) # prefetch from ring buffer
1146 lw $14,24($29) # prefetch from ring buffer
1211 lw $15,28($29) # prefetch from ring buffer
1276 lw $16,32($29) # prefetch from ring buffer
1341 lw $17,36($29) # prefetch from ring buffe
    [all...]
sha512-586.pl 71 my $prefetch=shift;
124 &movq ("mm6",&QWP(8*(9+16-14),"esp")) if ($prefetch);
127 &movq ("mm2",&QWP(8*(9+16-1),"esp")) if ($prefetch);
  /external/openssl/crypto/sha/asm/
sha256-mips.S 779 lw $8,0($29) # prefetch from ring buffer
832 lw $9,4($29) # prefetch from ring buffer
883 lw $10,8($29) # prefetch from ring buffer
951 lw $11,12($29) # prefetch from ring buffer
1016 lw $12,16($29) # prefetch from ring buffer
1081 lw $13,20($29) # prefetch from ring buffer
1146 lw $14,24($29) # prefetch from ring buffer
1211 lw $15,28($29) # prefetch from ring buffer
1276 lw $16,32($29) # prefetch from ring buffer
1341 lw $17,36($29) # prefetch from ring buffe
    [all...]
sha512-586.pl 71 my $prefetch=shift;
124 &movq ("mm6",&QWP(8*(9+16-14),"esp")) if ($prefetch);
127 &movq ("mm2",&QWP(8*(9+16-1),"esp")) if ($prefetch);
  /external/oprofile/events/i386/westmere/
unit_masks 115 0x01 requests L1D hardware prefetch requests
116 0x02 miss L1D hardware prefetch misses
117 0x04 triggers L1D hardware prefetch requests triggered
148 0x04 prefetch_clean L2 lines evicted by a prefetch request
149 0x08 prefetch_dirty L2 modified lines evicted by a prefetch request
161 0x40 prefetch_hit L2 prefetch hits
162 0x80 prefetch_miss L2 prefetch misses
170 0x08 prefetch L2 prefetch transactions
  /external/eigen/Eigen/src/SparseLU/
SparseLU_gemm_kernel.h 130 prefetch((A0+i+(5)*PacketSize));
131 prefetch((A1+i+(5)*PacketSize));
132 if(RK==4) prefetch((A2+i+(5)*PacketSize));
133 if(RK==4) prefetch((A3+i+(5)*PacketSize));
  /external/oprofile/events/i386/nehalem/
unit_masks 90 0x40 prefetch_hit Counts L2 prefetch hits for both code and data
91 0x80 prefetch_miss Counts L2 prefetch misses for both code and data
101 0x10 i_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i
102 0x20 s_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state
103 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state
104 0x80 m_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state
105 0xF0 mesi Counts all L2 prefetch requests
162 0x01 nta Counts number of SSE NTA prefetch/weakly-ordered instructions which missed the L1 data cache
165 0x01 requests Counts number of hardware prefetch requests dispatched out of the prefetch FIF
    [all...]
  /external/oprofile/events/mips/r10000/
events 9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
  /external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/
aes-parisc.pl 321 ldw 1024+0($tbl),%r0 ; prefetch te4
324 ldw 1024+32($tbl),%r0 ; prefetch te4
327 ldw 1024+64($tbl),%r0 ; prefetch te4
330 ldw 1024+96($tbl),%r0 ; prefetch te4
333 ldw 1024+128($tbl),%r0 ; prefetch te4
336 ldw 1024+160($tbl),%r0 ; prefetch te4
339 ldw 1024+192($tbl),%r0 ; prefetch te4
342 ldw 1024+224($tbl),%r0 ; prefetch te4
790 ldw 1024+0($tbl),%r0 ; prefetch td4
793 ldw 1024+32($tbl),%r0 ; prefetch td
    [all...]
aes-sparcv9.pl 370 ldx [$tbl+2048+0],%g0 ! prefetch te4
373 ldx [$tbl+2048+32],%g0 ! prefetch te4
376 ldx [$tbl+2048+64],%g0 ! prefetch te4
379 ldx [$tbl+2048+96],%g0 ! prefetch te4
382 ldx [$tbl+2048+128],%g0 ! prefetch te4
385 ldx [$tbl+2048+160],%g0 ! prefetch te4
388 ldx [$tbl+2048+192],%g0 ! prefetch te4
391 ldx [$tbl+2048+224],%g0 ! prefetch te4
916 ldx [$tbl+2048+0],%g0 ! prefetch td4
919 ldx [$tbl+2048+32],%g0 ! prefetch td
    [all...]
  /external/openssl/crypto/aes/asm/
aes-parisc.pl 321 ldw 1024+0($tbl),%r0 ; prefetch te4
324 ldw 1024+32($tbl),%r0 ; prefetch te4
327 ldw 1024+64($tbl),%r0 ; prefetch te4
330 ldw 1024+96($tbl),%r0 ; prefetch te4
333 ldw 1024+128($tbl),%r0 ; prefetch te4
336 ldw 1024+160($tbl),%r0 ; prefetch te4
339 ldw 1024+192($tbl),%r0 ; prefetch te4
342 ldw 1024+224($tbl),%r0 ; prefetch te4
790 ldw 1024+0($tbl),%r0 ; prefetch td4
793 ldw 1024+32($tbl),%r0 ; prefetch td
    [all...]
aes-sparcv9.pl 370 ldx [$tbl+2048+0],%g0 ! prefetch te4
373 ldx [$tbl+2048+32],%g0 ! prefetch te4
376 ldx [$tbl+2048+64],%g0 ! prefetch te4
379 ldx [$tbl+2048+96],%g0 ! prefetch te4
382 ldx [$tbl+2048+128],%g0 ! prefetch te4
385 ldx [$tbl+2048+160],%g0 ! prefetch te4
388 ldx [$tbl+2048+192],%g0 ! prefetch te4
391 ldx [$tbl+2048+224],%g0 ! prefetch te4
916 ldx [$tbl+2048+0],%g0 ! prefetch td4
919 ldx [$tbl+2048+32],%g0 ! prefetch td
    [all...]
  /external/linux-tools-perf/perf-3.12.0/arch/tile/lib/
memcpy_32.S 154 /* No need to prefetch dst, we'll just do the wh64
172 * This is our prefetch address. When we get near the end
188 /* Prefetch several lines ahead. */
195 /* Prefetch several lines ahead. */
202 /* Prefetch several lines ahead. */
213 * - r3 is the next prefetch address.
244 * to prefetch the last partial cache line (if any) just once, for the
246 * prefetch that line more than once, or subsequent prefetches
248 * branch to top of loop to execute final prefetch, and its
408 { prefetch r3; move r3, r8; slt_u r8, r8, r18
    [all...]

Completed in 2106 milliseconds

12 3 4 5 6