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  /external/llvm/test/CodeGen/Mips/msa/
3rf_4rf.ll 67 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
72 declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind
78 ; CHECK: fmsub.w
92 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
97 declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind
103 ; CHECK: fmsub.d
arithmetic_float.ll 152 ; CHECK-DAG: fmsub.w [[R1]], [[R2]], [[R3]]
172 ; CHECK-DAG: fmsub.d [[R1]], [[R2]], [[R3]]
  /external/llvm/test/CodeGen/AArch64/
arm64-fmadd.ll 23 ; CHECK: fmsub s0, s0, s1, s2
32 ; CHECK: fmsub s0, s1, s0, s2
66 ; CHECK: fmsub d0, d0, d1, d2
75 ; CHECK: fmsub d0, d1, d0, d2
fp-dp3.ll 21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
22 ; CHECK-NOFAST: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
61 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK-NOFAST: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
104 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
105 ; CHECK-NOFAST-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
157 ; CHECK-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
neon-scalar-by-elem-fma.ll 84 ; CHECK: {{fmls d[0-9]+, d[0-9]+, v[0-9]+.d\[0]|fmsub d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}}
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
gen-fma-test.py 56 opcodes1 = ['fmadd', 'fmsub', 'fnmadd', 'fnmsub']
  /external/valgrind/main/none/tests/ppc32/
jm-fp.stdout.exp 41 fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
42 fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
43 fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
44 fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
45 fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
46 fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
47 fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
48 fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
49 fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
50 fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e000030
    [all...]
round.stdout.exp     [all...]
round.c 33 FMSUB, FNMADD, FNMSUB, FSQRT
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
961 case FMSUB:
1096 case FMSUB:
1097 TERNOP("fmsub");
  /external/valgrind/main/none/tests/ppc64/
jm-fp.stdout.exp 41 fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
42 fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
43 fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
44 fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
45 fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
46 fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
47 fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
48 fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
49 fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
50 fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e000030
    [all...]
round.stdout.exp     [all...]
round.c 33 FMSUB, FNMADD, FNMSUB, FSQRT
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
961 case FMSUB:
1096 case FMSUB:
1097 TERNOP("fmsub");
  /external/vixl/doc/
changelog.md 34 + Fixed `smull`, `fmsub` and `sdiv` simulation.
supported-instructions.md 1201 ### fmsub ###
1205 void fmsub(const FPRegister& fd,
  /external/llvm/test/CodeGen/PowerPC/
fma.ll 26 ; CHECK: fmsub
  /external/llvm/test/MC/Mips/msa/
test_3rf.s 43 # CHECK: fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b]
44 # CHECK: fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b]
126 fmsub.w $w17, $w25, $w0
127 fmsub.d $w8, $w18, $w16
  /external/valgrind/main/auxprogs/
ppcfround.c 203 INSN(fmsub, "fmsub %%f4, %%f1,%%f2,%%f3");
204 INSN(fmsub_, "fmsub. %%f4, %%f1,%%f2,%%f3");
496 do_N_ternary("fmsub", insn_fmsub, macArgs, nMacArgs, SHOW_ALL);
  /external/llvm/test/MC/PowerPC/
ppc64-encoding-fp.s 206 # CHECK-BE: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38]
207 # CHECK-LE: fmsub 2, 3, 4, 5 # encoding: [0x38,0x29,0x43,0xfc]
208 fmsub 2, 3, 4, 5
209 # CHECK-BE: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39]
210 # CHECK-LE: fmsub. 2, 3, 4, 5 # encoding: [0x39,0x29,0x43,0xfc]
211 fmsub. 2, 3, 4, 5
  /external/llvm/test/MC/Disassembler/Mips/msa/
test_3rf.txt 43 0x79 0x40 0xcc 0x5b # CHECK: fmsub.w $w17, $w25, $w0
44 0x79 0x70 0x92 0x1b # CHECK: fmsub.d $w8, $w18, $w16
  /external/llvm/test/MC/Disassembler/PowerPC/
ppc64-encoding-fp.txt 186 # CHECK: fmsub 2, 3, 4, 5
189 # CHECK: fmsub. 2, 3, 4, 5
  /external/llvm/test/MC/Disassembler/AArch64/
arm64-scalar-fp.txt 54 # CHECK: fmsub s1, s2, s3, s4
55 # CHECK: fmsub d1, d2, d3, d4
  /external/llvm/test/MC/AArch64/
arm64-fp-encoding.s 52 fmsub s1, s2, s3, s4
53 fmsub d1, d2, d3, d4
55 ; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f]
56 ; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f]
  /external/llvm/lib/Target/PowerPC/
PPCSchedule.td 199 // fmsub IIC_FPFused
  /external/valgrind/main/
README.aarch64 146 FMADD/FMSUB/FNMADD/FNMSUB: generate and use the relevant fused
  /external/clang/test/CodeGen/
aarch64-neon-scalar-x-indexed-elem.c 117 // CHECK: {{fmls|fmsub}} {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+.d\[0\]|d[0-9]+}}

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