| /external/llvm/test/CodeGen/ARM/ |
| sxt_rot.ll | 5 ; CHECK: sxtb r0, r0
12 ; CHECK: sxtb r0, r0, ror #8
|
| fast-isel-icmp.ll | 38 ; ARM: sxtb r0, r0
39 ; ARM: sxtb r1, r1
42 ; THUMB: sxtb r0, r0
43 ; THUMB: sxtb r1, r1
|
| fast-isel-deadcode.ll | 15 ; THUMB-NOT: sxtb
|
| fast-isel-fold.ll | 78 ; ARM-NOT: sxtb
81 ; THUMB-NOT: sxtb
|
| fast-isel-ret.ll | 22 ; CHECK: sxtb r0, r0
|
| fast-isel-conversion.ll | 40 ; ARM: sxtb r0, r0
44 ; THUMB: sxtb r0, r0
86 ; ARM: sxtb r0, r0
90 ; THUMB: sxtb r0, r0
|
| fast-isel-ext.ll | 111 ; v7: sxtb r0, r0
121 ; v7: sxtb r0, r0
|
| fast-isel.ll | 104 ; THUMB: sxtb
108 ; ARM: sxtb
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-sxt_rot.ll | 6 ; CHECK: sxtb r0, r0
13 ; CHECK: sxtb.w r0, r0, ror #8
|
| thumb2-sxt-uxt.ll | 12 ; CHECK: sxtb
|
| /external/llvm/test/MC/ARM/ |
| thumb.s | 25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
|
| diagnostics.s | 310 sxtb r8, r3, #8
311 sxtb r8, r3, ror 24
312 sxtb r8, r3, ror #8 -
319 @ CHECK-ERRORS: sxtb r8, r3, #8
322 @ CHECK-ERRORS: sxtb r8, r3, ror 24
325 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
328 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fast-isel-icmp.ll | 147 ; CHECK: sxtb w0, w0
148 ; CHECK: sxtb w1, w1
170 ; CHECK: sxtb w0, w0
171 ; CHECK: sxtb w1, w1
195 ; CHECK: sxtb w0, w0
|
| addsub_ext.ll | 45 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
50 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
56 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
61 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
73 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb
|
| arm64-fast-isel-ret.ll | 48 ; CHECK: sxtb w0, w0
|
| arm64-fast-isel-call.ll | 41 ; CHECK: sxtb w0, w0
84 ; CHECK: sxtb w3, w[[REG2]]
|
| arm64-shifted-sext.ll | 45 ; CHECK: sxtb [[REG]], [[REG]]
91 ; CHECK: sxtb [[REG]], [[REG]]
136 ; CHECK: sxtb x[[REG]], w[[REG]]
|
| bitfield.ll | 11 ; CHECK: sxtb {{w[0-9]+}}, {{w[0-9]+}}
15 ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
128 ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
|
| arm64-fast-isel-conversion.ll | 111 ; CHECK: sxtb w0, w0
148 ; CHECK: sxtb x0, w[[TMP]]
256 ; CHECK: sxtb w0, w0
|
| /external/llvm/test/CodeGen/Thumb/ |
| ldr_ext.ll | 30 ; V6: sxtb
|
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 174 add w1, w2, w3, sxtb
183 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
191 add x1, x2, w3, sxtb
198 ; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
218 sub w1, w2, w3, sxtb
227 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
235 sub x1, x2, w3, sxtb
242 ; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
262 adds w1, w2, w3, sxtb
271 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| unpredictable-AExtI-arm.txt | 6 # CHECK: sxtb
|
| /external/vixl/doc/ |
| changelog.md | 35 + Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`.
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 177 # CHECK: add w1, w2, w3, sxtb
192 # CHECK: add x1, x2, w3, sxtb
219 # CHECK: sub w1, w2, w3, sxtb
234 # CHECK: sub x1, x2, w3, sxtb
261 # CHECK: adds w1, w2, w3, sxtb
276 # CHECK: adds x1, x2, w3, sxtb
299 # CHECK: subs w1, w2, w3, sxtb
314 # CHECK: subs x1, x2, w3, sxtb
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 45 SXTB,
64 case AArch64_AM::SXTB: return "sxtb";
131 case 4: return AArch64_AM::SXTB;
147 /// 100 ==> sxtb
158 case AArch64_AM::SXTB: return 4; break;
194 /// 100 ==> sxtb
|
